Abstract: A connector assembly for connection to a computer backpanel or the like includes a leadless integrated circuit package and a connector receptacle for receiving the leadless package. The leadless package has two insulating layers and outwardly extending conductors formed on each of the two layers. The insulating layers have contact coupling edges, with the contact coupling edge of one layer extending outwardly of the contact coupling edge of the other layer. Rows of contacts in the receptacle make electrical contact with the conductors on the leadless package at the contact coupling edges. In a second embodiment, the connector assembly includes a leadless integrated circuit package having three insulating layers and outwardly extending conductors formed on each of the three layers.

Abstract: A data processing system employing broadcast packet switching and having a plurality of subsystems and a system bus for linking the subsystems. The subsystems are grouped within stations that are each enclosed by a computer cabinet. The system bus includes a star coupler, first and second external transmission lines connecting each station to the star coupler, and first and second internal transmission lines within each station that are coupled to the first and second external transmission lines. The subsystems within each station are each coupled to the first and second internal transmission lines by a system bus interface. The system bus interface monitors the system bus for an idle condition, and passes a message from its subsystem to the system bus only when it detects an idle condition on the system bus. Each message on the system bus includes a postamble that is garbled by any system bus interface that detects an error in any message on the system bus.

Abstract: A data processing system that has a plurality of subsystems connected to a system bus includes diagnostic circuitry for isolating a fault at one of the subsystems. The diagnostic circuitry includes a multiplexer at the output gates of each subsystem to the system bus and diagnostic selection circuitry at a bus controller that provides a select signal to each multiplexer. When selected, the multiplexer is connected to pass a "high" logic level signal to an associated bit line of the system bus. When a bit line of the system bus is "stuck high," because of a fault at the output of one of the subsystems, the diagnostic circuitry selectively connects each subsystem to the bit line of the system bus in order to provide a "high" logic level signal to that bit line. A test interface and A/D converter are connected to the bit line, and if a voltage level change is detected after a subsystem is connected, the connected subsystem is not the one having the fault.

Abstract: A multilayer printed circuit board structure and a method for generating artwork masters for the manufacture thereof. The multilayer board comprises universal internal layers of predefined circuit patterns. The internal layers include power and ground planes, and for boards having high component and circuit density, one or two signal crossover layers with short, equal-length runs oriented transversely to the runs of an adjacent outermost signal layer. Electrical interconnections between layers of the circuit board are effected by interlayer conductors such as pins or plated-through holes at predefined locations. The artwork masters for the outermost layers are generated utilizing two degrees of layout precision. A universal layout master having interconnection pads and parallel circuit runs extending across the entire surface of the board is first prepared using a high degree of precision.

Abstract: A random number generator that provides bits at its output that are neither biased nor periodic. The generator includes a noise generator and sampling register that provide serial, randomly varying bits. A circuit within the generator for reducing auto-correlation or periodicity discards certain ones of the randomly varying bits, and includes a first shift register for receiving and storing the randomly varying bits and a second register for receiving in parallel and storing only a portion of the randomly varying bits from the first register. In order to eliminate bias, EXCLUSIVE OR gates are connected between the first and second registers in order to logically combine the randomly varying bits received by the second register with previous bits stored in the second register.

Abstract: Image formatting apparatus for a visual display where image data is stored in an addressable memory and is read out in selectable format with masking of desired areas of the display screen being controllable so as to change image contrast and/or to provide masked borders around selected images.

Abstract: A memory system having a word-addressable memory and bit changing circuitry for changing or updating individual bits within the data words stored in the memory. The memory includes a primary memory and a copy memory. The copy memory stores duplicates of the data words stored in the primary memory. The bit changing circuitry receives a word having a bit to be changed from the copy memory and returns the word, including the changed bit, to both the primary memory and copy memory.

Abstract: A self-correcting memory system includes internal error detection and correction circuitry that periodically accesses each data word and a group of ECC check bits associated with each data word stored in the memory system. The error detection and correction circuitry includes an ECC checking circuit that receives the accessed data word, generates ECC bits, and compares those ECC bits to the group of ECC check bits associated with the data word. The resulting signal is used to correct any single bit in error, and to indicate the presence of a double bit error. A self-correct address counter is cascaded to a refresh address counter in the control circuitry of the memory system so that the accessing of each data word occurs during a refresh cycle of the memory system.

Abstract: Diagnostic circuitry for use with the processor of a data processing system. The diagnostic circuitry includes a control register execution log for receiving control store addresses from a control register associated with an "EXECUTE+1" stage. A log pointer addresses the log when control store addresses are written into or read from the log. Test registers connected to the log and log pointer provide control store addresses and decrementing log addresses when the contents of the log are examined. One of the test registers is also used to hold a control store address for comparison with control store addresses of executing microinstructions, and when a match occurs, to generate a SYNC signal.

Abstract: A cache memory has a data buffer for storing blocks of data from a main memory and an index for storing main memory addresses associated with the data blocks in the data buffer. The size of the blocks of data stored in the data buffer can be varied in order to increase the "hit ratio" of the cache memory. The index is a set associative memory and bits provided to an address input of the index are selectively inhibited by an address inhibit circuit when the size of the data blocks in the data buffer is to be varied. A block size register stores block size information that is provided to the address inhibit circuit. The block size information is also provided to a fetch generate counter and a fetch return counter that control the number of words transferred as a block from the main memory to the cache memory.

Abstract: Parity prediction circuitry for use with a multifunction register. The parity prediction circuitry includes a parity prediction circuit associated with each function of the register. A selecting multiplexer selects the parity prediction circuit that will provide a predicted parity bit at the output of the parity prediction circuitry, with the selection controlled by the same control signals that select the function of the register. The parity prediction circuits associated with COUNT UP and COUNT DOWN functions also include a multiplexer, with this multiplexer having data inputs connected in a predetermined fashion to signals having a value of either logic level "1" or logic level "0". This multiplexer has control inputs connected to the data outputs of the register and has a data output selected by the control inputs in order to provide a signal indicating whether the predicted parity is to change from the previous predicted parity.

Abstract: A data recovery circuit for use in a data processing system where plural subsystems are linked by a bit serial transmission line. The data transmitted over the bit serial transmission line is in the form of a phase encoded (PE) pulse signal. The data recovery circuit includes a time delay circuit for delaying the PE pulse signal by a three-quarter bit period. The three-quarter bit period delay signal permits the generation of a control clock signal. The control clock signal is used in sampling the PE pulse signal at three-quarter bit period points in order to generate a control signal that indicates the absence or presence of a transition at the midpoint of each bit period of the PE pulse signal. The control signal is used to generate a recovered clock signal by logically combining the control signal with the PE pulse signal and a one-half bit period delayed PE pulse signal.

Abstract: A register circuit capable of use in various components of a computer. The register circuit includes two registers and logic circuitry that enables plural data buses to be selectively connected in various configurations to the data inputs and outputs of the registers. In an embodiment showing the register circuit constructed using emitter coupled logic, a clocking circuit generates clocking signals for selecting the data buses to be connected to the input of each register. Each register comprises plural master-slave flip-flops which receive the clocking signals from the clocking circuit and operatively connect the flip-flops to the selected bus or buses in response to such signals.

Abstract: An encoder/decoder is provided having two random bit generators which are cross-coupled in the Encoding mode with the data signal being directed to the input of each random bit generator. The data signal is also logically combined with the output of each random bit generator. In the Decoding mode the random bit generators are connected in a feedback configuration and the to-be-decoded signal is directed to the input of each random bit generator. The to-be-decoded signal is also logically combined with the output of each random bit generator to provide the decoded signal.

Abstract: A data processing system having optically linked subsystems, including an optical keyboard. The optical keyboard includes sequentially strobed LED's arranged to provide intersecting light paths in an X-Y matrix. A key on the keyboard is associated with each intersection of the light paths. When the key is depressed, the optical signals on the intersecting light paths are blocked. The resulting coded optical signals are used directly in transmitting to another subsystem the data entered at the keyboard.

Abstract: A processor having a pipeline architecture is comprised of a plurality of replaceable circuit units and includes a snapshot circuit associated with each replaceable circuit unit. Each snapshot circuit has a snapshot register for storing the signals at test points in its associated replaceable circuit unit in response to either an immediate snapshot command or a delayed snapshot command being executed by a processor. A command-under-test passing through the processor results in the signals at the test points. The delayed snapshot command delays the storing of the signals by the snapshot register so that by preceding the command-under-test by a delayed snapshot command, the signals at test points in the execute stage of the processor are stored during the execution of the command-under-test.

Abstract: A multilayer printed circuit board having a pad pattern formed on each of the layers. When the board is assembled, the layers are releasably secured together. The pads on each layer are aligned and make electrical contact with the pads on adjacent layers to provide interlayer electrical connections.

Abstract: A digital phase lock circuit wherein both the phase and frequency of an output signal are synchronized to an input signal. The present phase lock circuit is comprised of a clock signal source, first, second, and third counters, and a holding register. The first counter is utilized to count a predetermined number of cycles of the input signal to establish a first time period. The second counter receives as another input the clock signal and counts the clocks during the established first time period. The value of counted clocks contained in the second counter at the end of the first time period is divided by the predetermined number of cycles the first counter is set to count, and the result is stored in the holding register. The count in the holding register is used to preset the third counter which is then allowed to count down to zero, at the clock rate. The third counter is preset to the value contained in the holding register at each establishment of the first time period.

Abstract: An optically linked distributed data processing system having a plurality of stations and first and second transmission lines associated with each station. The first transmission line carries optical signals to its associated station and the second transmission line carries optical signals from its associated station. An active optical coupler module couples each first transmission line to every second transmission line. The coupler module includes a tapered waveguide for directing the optical signals from each of the first transmission lines to a single optical path, an optical detector for converting the optical signals to electrical signals, an amplifier for amplifying the electrical signals. In one embodiment a single optical source converts the amplified electrical signals back to optical signals, and in a second embodiment a plurality of optical sources, one for each of the second transmission lines, convert the amplified electrical signals back to optical signals.

Abstract: A data processing system having a plurality of stations and an optical transmission bus linking the stations. The bus includes two transmission lines carrying optical signals in opposite directions so that two stations may communicate simultaneously. A passive optical coupler module couples each station to the two transmission lines. The optical coupler module includes a silicon substrate having suitably formed grooves and recesses for mounting single fiber waveguide segments, tapered waveguides, each for directing the optical signal on either of two waveguide segments to a single optical path, and optical beam splitters, each for splitting a portion of the optical signal on a waveguide segment for each of two other waveguide segments.