Patents Represented by Attorney, Agent or Law Firm Stephen G. Stanton
  • Patent number: 8337820
    Abstract: A topical skin care dihydroxyacetone-free final gel formulation to protect skin from ultraviolet rays comprising dispersed: titanium dioxide; 5-hydroxy-tryptophan; histidine; and N-acetyl-tyrosine.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: December 25, 2012
    Inventor: Bart Nieuwenhuijsen
  • Patent number: 8216555
    Abstract: The object of the invention is to provide a topical preparation for (acne) rosacea and other sensitive skin types that protects the face from harmful UV rays without the use of chemical sunscreen ingredients. It has long been found that chemical sunscreen ingredients (most popular are oxybenzone and avobenzone) can cause an increase of rosacea symptoms (flushing, erythema, papules) (Nedorost (2003) and Landers et al., 2003). Furthermore, typical waterproof sunscreen preparations also contain various forms of silicones that are used to increase the hydrophobicity of the sunscreen. These waterproof sunscreen preparations impair the release of heat from the skin. The combination of this “trapped heat” and a sensitivity to chemical sunscreen ingredients, is harmful to rosacea skin. Therefore, a sunscreen preparation that is water-soluble and uses alternative UV absorbing and UV scattering ingredients would be very useful in protecting rosacea skin from harmful UV rays.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: July 10, 2012
    Inventor: Bart Willem Nieuwenhuijsen
  • Patent number: 8087272
    Abstract: A locking mechanism is provided that has an unlocked position and a locked position. The locking mechanism comprises the following. A first handle. A first rose attached to the first handle with the first handle adapted for rotational movement relative to the first rose. A first longitudinal slot in the first rose. A locking cartridge cylinder at least partially contained within at least the first handle or the first rose. A locking tab operably connected to the locking cartridge cylinder adapted for movement: at least partially into at least the second slot in the first rose in a locked position; and completely out of the first longitudinal slot in the first rose in an unlocked position.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: January 3, 2012
    Inventor: Fouad F. Korban
  • Patent number: 6835631
    Abstract: A method of enhancing inductor performance comprising the following steps. A structure having a first oxide layer formed thereover is provided. A lower low-k dielectric layer is formed over the first oxide layer. A second oxide layer is formed over the lower low-k dielectric layer. The second oxide layer is patterned to form at least one hole there through exposing a portion of the lower low-k dielectric layer. Etching through the exposed portion of the lower low-k dielectric layer and into the lower low-k dielectric layer to from at least one respective air gap within the etched lower low-k dielectric layer. An upper low-k dielectric layer is formed over the patterned second oxide layer. At least one inductor is formed within the upper low-k dielectric layer and over the at least one air gap whereby the performance of the inductor is enhanced.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: December 28, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd
    Inventors: Zheng Jia Zhen, Sanford Chu, Ng Chit Hwei, Lap Chan, Purakh Raj Verma
  • Patent number: 6835609
    Abstract: A method of forming a double gated SOI channel transistor comprising the following steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI silicon oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned silicon layer. A dummy layer is formed over the SOI silicon oxide layer and the patterned SOI silicon layer. The dummy layer is patterned to form a damascene opening therein exposing: a portion of the lower SOI silicon oxide layer; and a central portion of the patterned SOI silicon layer to define a source structure and a drain structure. Patterning the exposed lower SOI silicon oxide layer to form a recess. Gate oxide layer portions are formed around the exposed portion of the patterned SOI silicon layer. A planarized layer portion is formed within the final damascene opening. The planarized layer portion including a bottom gate and a top gate.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: December 28, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yong Meng Lee, Da Jin, Mau Lam Lai, David Vigar, Siow Lee Chwa
  • Patent number: 6828082
    Abstract: A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: December 7, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chew-Hoe Ang, Eng Hua Lim, Randall Cha, Jia-Zhen Zheng, Elgin Quek, Mei-Sheng Zhou, Daniel Yen
  • Patent number: 6821888
    Abstract: A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.
    Type: Grant
    Filed: February 13, 2002
    Date of Patent: November 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yakub Aliyu, Simon Chooi, Meisheng Zhou, John Sudijono, Subhash Gupta, Sudipto Ranendra Roy
  • Patent number: 6822268
    Abstract: A method of fabricating an LCD-on-silicon pixel device, comprising the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: November 23, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yung-Tao Lin, Sik On Kong
  • Patent number: 6821892
    Abstract: A method is disclosed for accurately predicting the wet etch end points as a function of the temperature and concentration of the etching solution, as well as of the thickness of the film to be etched. This is accomplished by fitting an etch rate equation to the process of etching a film in terms of two constant parameters that are determined by one set of experiments performed on a given wet etch bench. Thereafter, the constants are used with the rate equation to calculate precisely the etch rate of a film, and then the etch rate is divided into a target film loss or a target film thickness to obtain etching time, or time to etch, which takes into account the variations in temperature and concentration, for example, of the acid in the solution. The resulting film either looses the specified amount of material, or acquires the specified thickness without incurring any damage, which is especially suited for sub-micron semiconductor technology where precise etching is required.
    Type: Grant
    Filed: June 4, 2001
    Date of Patent: November 23, 2004
    Assignee: Promos Technologies, Inc.
    Inventors: Chun Hong Peng, Rex Chen, Simon Chang
  • Patent number: 6806136
    Abstract: The present invention relates generally to semiconductor fabrication and more specifically to simultaneous formation of capacitors, resistors and metal oxide semiconductor.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: October 19, 2004
    Assignee: Episil Technologies, Inc.
    Inventor: Hsiu-Wen Hsu
  • Patent number: 6802945
    Abstract: A method of forming a device, comprising the following steps. A wafer holder and inner walls of a chamber are coated with a seasoning layer The wafer is placed upon the wafer holder and is cleaned wherein a portion of the seasoning layer is re-deposited upon the wafer over and between adjacent wafer conductive structures. The wafer is removed from the chamber and at least two adjacent upper metal structures are formed over at least one portion of a metal barrier layer. The exposed portions of the metal barrier layer are etched and removed, exposing portions of the re-deposited seasoning layer portions using the metal barrier layer etch process which also removes any exposed portions of the re-deposited seasoning layer portions that are comprised of a material etchable in the metal barrier layer etch process.
    Type: Grant
    Filed: January 6, 2003
    Date of Patent: October 12, 2004
    Assignee: Megic Corporation
    Inventors: Hsien-Tsung Liu, Chien-Kang Chou, Ching-San Lin
  • Patent number: 6790374
    Abstract: A method for forming an etched silicon layer. There is first provided a first substrate having formed thereover a first silicon layer. There is then etched the first silicon layer to form an etched first silicon layer while employing a plasma etch method employing a plasma reactor chamber in conjunction with a plasma etchant gas composition which upon plasma activation provides at least one of an active bromine containing etchant species and an active chlorine containing etchant species.
    Type: Grant
    Filed: November 18, 1999
    Date of Patent: September 14, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Kwok Keung Paul Ho, Xuechun Dai
  • Patent number: 6787404
    Abstract: A method of forming a double-gated transistor comprising the following sequential steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned SOI silicon layer including a source region and a drain region connected by a channel portion. An encasing oxide layer is formed over the patterned SOI silicon layer to form an encased patterned SOI silicon layer. A patterned dummy layer is formed over the encased patterned SOI silicon layer. The patterned dummy layer having an opening, with exposed side walls, exposing: the channel portion of the encased patterned SOI silicon layer; and portions of the upper surface of the SOI oxide layer. Offset spacers are over the exposed side walls of the patterned dummy layer opening.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: September 7, 2004
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yong Meng Lee, Da Jin, David Vigar
  • Patent number: 6784002
    Abstract: A wafer bumping method comprising the following steps of. A wafer having fields is provided. The wafer having at least one wafer identification character formed thereon within one or more of the fields. A dry film resist is formed over the wafer. Portions of the dry film resist are selectively exposed field by field using a mask whereby the mask is shifted over the one or more fields containing the at least one wafer identification character so that the one or more fields containing the at least one wafer identification character is double exposed after the mask shift so that all of the one or more fields containing the at least one wafer identification character is completely exposed. The selectively exposed dry film resist is developed to remove the non-exposed portions of the dry film resist.
    Type: Grant
    Filed: June 21, 2002
    Date of Patent: August 31, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Hui-Peng Wang, Kuo-Wei Lin, Hwei-Mei Yu, Ta-Yang Lin, Charles Tseng
  • Patent number: 6777318
    Abstract: A method of forming at least one aluminum/copper clad interconnect comprising the following steps. A substrate is provided having an overlying patterned dielectric layer. The patterned dielectric layer having at least one lower opening. The at least one lower opening is lined with a first barrier layer. At least one planarized copper portion is formed within the at least one first barrier layer lined lower opening. A patterned layer is formed over the at least one planarized copper portion and the patterned dielectric layer. The patterned layer has at least one upper opening exposing at least a portion of the at least one planarized copper portion. The at least one upper opening is lined with a second barrier layer. At least one aluminum portion is formed within the at least one second barrier layer lined opening to form the at least one aluminum/copper clad interconnect.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: August 17, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shin-Puu Jeng, Shang-Yun Hou
  • Patent number: 6777347
    Abstract: A method for forming porous silicon oxide film, comprising the following steps. A CVD chamber having inner walls and a wafer chuck/heater is provided. At least a portion of the CVD chamber inner walls is pre-coated with a layer of first PECVD silicon oxide film having a first thermal CVD oxide deposition rate thereupon. A semiconductor wafer is placed on the wafer chuck/heater within pre-coated CVD chamber. The semiconductor wafer including an upper second PECVD silicon oxide film having a second thermal CVD oxide deposition rate thereupon that is less than the first thermal CVD oxide deposition rate upon the first PECVD silicon oxide film coating the CVD chamber inner walls. A porous silicon oxide film is deposited upon the upper second PECVD silicon oxide film overlying the semiconductor wafer. The porous silicon oxide film being different from the first PECVD silicon oxide film coating the CVD chamber inner walls.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: August 17, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chyi-Tsong Ni, Eric Su
  • Patent number: 6753210
    Abstract: A method of forming a metal fuse comprising the following steps. A structure is provided having exposed adjacent metal structures. A patterned dielectric layer is formed over the structure. The patterned dielectric layer having via openings 2exposing at least a portion of the exposed adjacent metal structures. A metal fuse portion is formed between at least two of the adjacent metal structures without additional photolithography, etch or deposition processes. The metal fuse portion including a portion having a nominal mass and a sub-portion of the portion having a mass less than the nominal mass so that the metal fuse portion is more easily disconnected at the less massive sub-portion during programming of the metal fuse portion.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: June 22, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Shin-Puu Jeng, Chi-Hsi Wu, Shang Y. Hou
  • Patent number: 6750082
    Abstract: A method of assembling a package having an exposed die comprising the following steps. A die attached to a substrate by connectors is provided. The die having a backside. Encapsulate is formed around the die and over the backside of the die to form an encapsulated package. The encapsulate overlying the backside of the die and a portion of the backside of the die are removed using a backside exposure process to complete the assembled package having the die exposed.
    Type: Grant
    Filed: September 13, 2002
    Date of Patent: June 15, 2004
    Assignee: Advanpack Solutions Pte. Ltd.
    Inventors: John Briar, Roman Perez, Tan Kim Hwee
  • Patent number: 6746966
    Abstract: A method of unblinding an alignment mark comprising the following steps. A substrate having a cell area and an alignment mark within an alignment area is provided. An STI trench is formed into the substrate within the cell area. A silicon oxide layer is formed over the substrate, filling the STI trench and the alignment mark. The silicon oxide layer is planarized to form a planarized STI within the STI trench and leaving silicon oxide within the alignment mark to form a blinded alignment mark. A wet chemical etchant is applied within the alignment mark area over the blinded alignment mark to at least partially remove the silicon oxide within the alignment mark. The remaining silicon oxide is removed from within the blinded alignment mark to unblind the alignment mark. A drop etcher apparatus is also disclosed.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: June 8, 2004
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chung-Long Chang, Henry Lo, Shang-Ting Tsai, Yu-Liang Lin
  • Patent number: 6740471
    Abstract: A method of improving photoresist adhesion in a reworked device, including the following steps. A semiconductor structure having an upper exposed metal layer is provided. An ARC layer is formed over the upper exposed metal layer. The ARC layer having an upper surface. A first photoresist layer is formed upon the ARC layer. The first photoresist layer is removed by a rework process. The ARC layer upper surface is roughened to form a roughened ARC layer upper surface. A second photoresist layer is formed upon the roughened ARC layer upper surface whereby adhesion of the second photoresist layer to the ARC layer is improved.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: May 25, 2004
    Inventors: Gau-Ming Lu, Dowson Jang, Wen-Han Hung, Yeong-Rong Chang