Abstract: A method for forming a trench having upper rounded corners comprising the following steps. A substrate having an oxide layer formed thereover is provided. A hard mask layer is formed over the oxide layer. A patterned patterning layer is formed over the hard mask layer leaving one or more portions of the hard mask layer exposed. The hard mask layer is patterned using the patterned patterning layer as a mask to form a patterned hard mask layer having one or more openings exposing one or more portions of the oxide layer. The patterned patterning layer is removed. The oxide layer is patterned using the patterned hard mask layer as a mask using a first trench etching process to etch through the oxide layer at the one or more exposed portions of the oxide layer and into the substrate to form one or more shallow trenches within the substrate having upper rounded corners at the respective interfaces between substrate and patterned oxide layer.

Abstract: A method of fabricating a dual-oxide STI comprising the following steps. A structure having an STI opening formed therein is provided. An HDP silicon oxide layer portion is formed within the STI opening, partially filling the STI opening. A planarized HDP silicon-rich-oxide cap layer is formed upon the HDP silicon oxide layer portion, filling the STI opening to form the dual-oxide STI, whereby any unlanded contact window formed through an overlying interlevel dielectric layer exposing a portion of the dual-oxide STI only exposes a portion of the HDP silicon-rich-oxide cap layer.

Abstract: A method of simultaneously forming a high-k metal oxide dielectric layer and a gate oxide dielectric layer comprising the following steps. A structure having isolation regions which separate the structure into at least one core device active region and one I/O active region is provided. A buffer layer is formed over the structure and the isolation regions. A metal containing layer is formed over the buffer layer. The metal containing layer and the buffer layer are patterned to: form an exposed patterned metal containing layer within the at least one core device action region; and expose the structure within the at least one I/O active region. The exposed patterned metal containing layer and the exposed structure within the at least one I/O active region are oxidized to simultaneously form: the high-k metal oxide dielectric layer within the at least one core device active region; and the gate oxide dielectric layer within the at least one I/O active region.

Abstract: A semiconductor chip device package comprised of a semiconductor substrate having semiconductor devices formed on the semiconductor substrate. At least one dielectric layer is over the semiconductor substrate. At least one layer of interconnects is over the semiconductor devices and within the at least one respective dielectric layer with at least a portion of the interconnects being separated by voids having a vacuum or air therein. A passivation layer is over the uppermost of the at least one layer of interconnects. Wherein the semiconductor chip device is vacuum sealed within a semiconductor chip device package.

Abstract: A method for etching a dielectric layer comprising the following steps. A structure having a low-k dielectric layer formed thereover is provided. A DARC layer is formed over the low-k dielectric layer. A patterned masking layer is formed over the DARC layer. Using the patterned masking layer as a mask, the DARC layer and the low-k dielectric layer are etched employing an CHxFy/O2/N2/Ar etch chemistry.

Abstract: A method for forming a patterned layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable layer, where the oxygen containing plasma etchable layer is formed of a carbon and fluorine containing material. There is then formed over the oxygen containing plasma etchable layer a mask layer. There is then etched through use an oxygen containing plasma etch method while employing the mask layer as an etch mask layer the oxygen containing plasma etchable layer to form a patterned oxygen containing plasma etched layer, where the oxygen containing plasma etch method employs an etchant gas composition comprising an oxygen containing etchant gas and a fluorine containing etchant gas.

Abstract: A method of fabricating a dual-damascene structure comprising the following steps. A structure having a patterned low-k material layer formed thereover is provided. The patterned low-k material layer having an upper surface and at least one via hole formed therethrough. A plug material layer is formed over the patterned low-k material layer and filling the at least one via hole. The plug material layer being comprised of a material dissolvable in TMAH or deionized water. The plug material layer is developed to form a plug within the respective at least one via hole having a height below the upper surface of the patterned low-k material layer. The plug is baked to crosslink the plug material comprising the plug. A trench masking layer is formed and patterned to form a patterned trench masking layer having at least one trench substantially centered over the respective at least one via hole and exposing a portion of patterned low-k material layer adjacent the at least one via hole.

Abstract: A method of fabricating an HV-I/O ESD MOS device comprising the following steps. A structure having a first device region, a second device region and an HV-I/O ESD MOS device region is provided. A gate is formed over an oxide layer within the first device region. A gate is formed over an oxide layer within the second device region. A gate is formed over an oxide layer within the HV-I/O ESD MOS device region. The first device gate oxide layer is thinner than the second device gate oxide layer and the HV-I/O ESD MOS device gate oxide layer. The gate and oxide layers within each region have exposed side walls. An LV-LDD mask is formed over the gate and the structure within the second device region. An LV-LDD implant is performed into the structure adjacent the first device gate and the HV-I/O ESD MOS device gate to form first device LV-LDD implants and HV-I/O ESD MOS device LV-LDD implants. The LV-LDD mask is removed. An HV-LDD mask is formed over the gate and the structure within the first device region.

Abstract: A method for reducing contaminants in a processing chamber 10 having chamber plasma processing region components comprising the following steps. The chamber plasma processing region components are cleaned. The chamber is then seasoned as follows. A first USG layer is formed over the chamber plasma processing region components. An FSG layer is formed over the first USG layer. A second USG layer is formed over the FSG layer. Wherein the USG, FSG, and second USG layers comprise a UFU season film. A UFU season film coating the chamber plasma processing region components of a processing chamber comprises: an inner USG layer over the chamber plasma processing region components; an FSG layer over the inner USG layer; and an outer USG layer over the FSG layer.

Abstract: A method of patterning a gate electrode layer having an underlying high-k dielectric layer comprising the following sequential steps. A substrate is provided. A high-k dielectric layer is formed over the substrate. A gate electrode layer is formed over the high-k dielectric layer. The gate electrode layer is patterned to form a patterned gate electrode layer, the patterned gate electrode layer having exposed side walls and a top. Sidewall spacers are formed over the exposed side walls of the patterned gate electrode layer, the sidewall spacers having tops. The patterned gate electrode layer is etched to pull the top of the patterned gate electrode layer down from the tops of the sidewall spacers. The exposed portions of the high-k dielectric layer not under the sidewall spacers and the pulled-down patterned gate electrode layer are removed.

Abstract: A method of forming a dual damascene opening, comprising the following steps. A semiconductor structure having at least one exposed metal line is provided. A spin-on-polymer layer is formed over the semiconductor structure and the metal line. A CVD low-k material layer is formed over the spin-on-polymer layer. The CVD low-k material layer is patterned to form a CVD low-k material layer via over the metal line. The spin-on-polymer layer is patterned to form a spin-on-polymer layer via opening continuous and contiguous with the CVD low-k material layer via and exposing a portion of the metal line. The CVD low-k material layer adjacent the CVD low-k material layer via is patterned to form a CVD low-k material layer trench. The spin-on-polymer layer via opening and the CVD low-k material layer trench forming a dual damascene opening.

Abstract: A method of fabricating an air-gap spacer of a semiconductor device, comprising the following steps. A semiconductor substrate having at least a pair of STIs defining an active region is provided. A gate electrode is formed on the substrate within the active region. The gate electrode having an underlying gate dielectric layer. A liner oxide layer is formed over the structure, covering the sidewalls of the gate dielectric layer, the gate electrode, and over the top surface of the gate electrode. A liner nitride layer is formed over the liner oxide layer. A thick oxide layer is formed over the structure. The thick oxide, liner nitride, and liner oxide layers are planarized level with the top surface of the gate electrode, and exposing the liner oxide layer at either side of the gate electrode.

Abstract: A method of fabricating a dual gate electrode CMOS device having dual gate electrodes. An N+ poly gate is used for the nMOSFET and a metal gate is used for the pMOSFET. The N+ nMOSFET poly gate may be capped with a highly conductive metal to reduce its gate resistance. A sacrificial cap is used for the N+ poly gate to eliminate a mask level for the dual gate electrodes.

Abstract: A method of forming an inverted staircase shaped STI structure comprising the following steps. A semiconductor substrate having an overlying oxide layer is provided. The substrate having at least a pair of active areas defining an STI region therebetween. The oxide layer is etched a first time within the active areas to form first step trenches. The first step trenches having exposed sidewalls. Continuous side wall spacers are formed on said exposed first step trench sidewalls. The oxide layer is etched X+1 more successive times using the previously formed step side wall spacers as masks to form successive step trenches within the active areas. Each of the successive step trenches having exposed sidewalls and have side wall spacers successively formed on the successive step trench exposed sidewalls. The oxide layer is etched a final time using the previously formed step side wall spacers as masks to form final step trenches exposing the substrate within the active areas.

Abstract: A method of removing remaining photoresist over an Al or Al alloy structure after etching the Al or Al alloy structure in chlorine based plasma, the Al or Al alloy structure being over a substrate, comprises the following steps. The photoresist, Al or Al alloy structure, and the substrate are treated in-situ with organic solvent vapors (such as acetone or carbon tetrachloride) in the absence of plasma excitation at a first predetermined temperature and pressure. The remaining photoresist is then removed with a plasma activated oxygen flow at a second predetermined temperature and pressure.

Abstract: A method for dry plasma selective etching of a pattern in a silicon nitride dielectric layer formed over a semiconductor substrate employed within a microelectronics fabrication. There is provided a semiconductor substrate having formed thereupon a pad oxide layer over which is formed a silicon nitride dielectric layer. There is formed over the substrate a patterned photoresist etch mask layer. There is then selectively etched the pattern of the photoresist etch mask layer into the silicon nitride layer employing a four-step etching process with three plasma etching environments which include; (1) a “break-through” etching step; (2) a “bulk” etching step to remove a majority of the silicon nitride layer and a “buffer” etching step to remove the remainder of the silicon nitride layer; and (3) an “over-etch” step to complete removal of silicon nitride without excessive etching of underlying material.

Abstract: A first option is a method of forming an ultra thin buffer oxide layer comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided. The silicon substrate has an upper surface. A sacrificial oxide layer is formed over the silicon substrate and the STI regions. Oxygen is implanted within the silicon substrate. The oxygen implant having a peak concentration proximate the upper surface of the silicon substrate. The sacrificial oxide layer is stripped and removed. A gate dielectric layer is formed over the silicon substrate. A conductor layer is deposited over the gate dielectric layer. The structure is annealed to form ultra-thin buffer oxide layer between the silicon substrate and the gate dielectric layer. A second option is a method of forming an ultra-thin buffer oxide layer, comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided.

Abstract: A method of cleaning a low-k material etched opening, comprising the following steps. A semiconductor structure having an exposed device therein is provided. An etch stop layer is formed over the semiconductor structure and the exposed device. A layer of low-k material is formed over the etch stop layer semiconductor structure and device. A patterned layer of photoresist is formed over the low-k material layer. The patterned photoresist layer is used as a mask to etch low-k material layer is etched to form an opening exposing at least a portion of the etch stop layer over the device. The patterned photoresist layer is removed by a low temperature ashing process at a temperature from about 23 to 27° C., and more preferably about 25° C. (room temperature). The exposed portion of the etch stop layer over the device is removed to expose the underlying device by a low pressure, low bias etching process at a pressure from about 8 to 12 milli-Torr and a bias power from about 25 to 35 W.

Abstract: A method of fabricating a vertical channel transistor, comprising the following steps. A semiconductor substrate having an upper surface is provided. A high doped N-type lower epitaxial silicon layer is formed on the semiconductor substrate. A low doped P-type middle epitaxial silicon layer is formed on the lower epitaxial silicon layer. A high doped N-type upper epitaxial silicon layer is formed on the middle epitaxial silicon layer. The lower, middle, and upper epitaxial silicon layers are etched to form a epitaxial layer stack defined by isolation trenches. Oxide is formed within the isolation trenches. The oxide is etched to form a gate trench within one of the isolation trenches exposing a sidewall of the epitaxial layer stack facing the gate trench. Multi-quantum wells or a stained-layer super lattice is formed on the exposed epitaxial layer stack sidewall. A gate dielectric layer is formed on the multi-quantum wells or the stained-layer super lattice and within the gate trench.

Abstract: A method for forming dual thickness gate oxide layers comprising the following steps. A structure having at least a first area and a second area is provided. The second area of the structure is masked. Ion implanting Si4+ or Ge4+ ions into the unmasked first area of the structure to form an amorphous layer within the first area of the structure. The second area of the structure is unmasked. The first and second areas of the structure are oxidized to form: a first gate oxide layer upon the structure within the first area; and a second gate oxide layer upon the structure within the second area. The first gate oxide layer having a greater thickness than the second gate oxide layer, completing formation of the dual thickness gate oxide layers.