Abstract: One embodiment of the present invention includes a method for controlling a gain of a wideband signal. The method comprises adding a virtual channel to the wideband signal, the wideband signal comprising at least one channel. The method also comprises monitoring an output power associated with the wideband signal that includes the at least one channel and the virtual channel. The method further comprises setting a gain factor to achieve a predetermined output power of the wideband signal and amplifying the wideband signal based on the gain factor.
Abstract: In at least some embodiments, a system may comprise one or more devices configurable to communicate according to a first protocol that permits interpretation of transmitted symbols associated with a first time duration. The system may further comprise one or more devices configurable to communicate according to a second protocol that permits interpretation of transmitted symbols associated with multiple time durations. The one or more devices configurable to communicate according to the second protocol are operable to communicate using transmitted symbols associated with the first time duration and to communicate using transmitted symbols associated with a time duration that is not supported by the one or more devices configured to communicate according to the first protocol.
Type:
Grant
Filed:
August 11, 2008
Date of Patent:
June 29, 2010
Assignee:
Texas Instruments Incorporated
Inventors:
Markos G. Troulis, Arndt Joseph Mueller, Karl E. Fitzke
Abstract: A wireless receiver operating in a wireless communication environment in which a beginning of a packet contains a repetitive sequence. The wireless receiver may compute a variance (example of a measure of variations in the cross correlation values) of cross-correlation values obtained by cross correlating a received signal and a copy of the preamble sequence starting at different time instances. When a valid packet is received, the variance of the values resulting from the cross correlation is high, otherwise the variance is low. As a result packet detection is made robust, and false packet detection due to interference signals is reduced. In an embodiment, the wireless receiver is implemented in the context of WLAN 802.11 a/g network.
Abstract: A deterministic access system and method is provided that may be used for gaining access to a shared communication medium in a mesh or decentralized network. The deterministic access method enables QoS prioritization for periodic data flows such as those used in streaming media or VOIP communications without the direction of a central controller. The method provides a way for network nodes to schedule communications that take into account the hidden node problem, provide priority access to the communication medium for high QoS data flows, and provide shared access to the medium for lower priority data packets during unscheduled times. The method also enables both backward and forward compatibility with network communication methods as well as interoperability between mesh networks and conventional networks.
Abstract: A novel mechanism for sharing filter taps across a plurality of interference cancellers. Each interference canceller may be directed to impairment, such as Ethernet impairments, including Ethernet 1000Base-T impairments. Various interference impairments include echo cancellation, NEXT cancellation and/or other interference detection or cancellation, etc. The hardware requirements of the interference impairment cancellers are reduced by sharing filter taps among the cancellers. In a first embodiment, the taps from a unified filter tap bank are shared across all the interference impairment cancellers for all four channels and over all ports. In a second embodiment, a portion of the taps of each filter are shared wherein each canceller comprises a fixed filter tap portion and a shared filter tap portion. A tap allocation algorithm assigns taps to those cancellers that need them the most. A canceller configuration is selected that yields maximal interference mitigation and the taps are allocated accordingly.
Type:
Grant
Filed:
April 12, 2006
Date of Patent:
June 15, 2010
Assignee:
Texas Instruments Incorporated
Inventors:
Daniel Sharon, Itay Lusky, Kobi Haim, Nohik Semel, Rafi Dalla Torre
Abstract: A novel and useful baseline wander correction mechanism for use with transformer coupled baseband communication receivers. Parametric estimation of the transformer model is used estimate and cancel the baseline wander effect. A parametric model is used to model the baseline wander impairment created by the transmitter and receiver transformers as a high pass filter having an exponential decay parameter alpha. A correction signal for both the far end and echo signal paths are calculated and summed to generate a total correction signal. The total correction signal is partitioned into an analog correction signal that is applied to the analog portion of the communications receiver and into a digital correction signal that is similarly applied to the analog portion of the communications receiver.
Type:
Grant
Filed:
December 28, 2006
Date of Patent:
June 15, 2010
Assignee:
Texas Instruments Incorporated
Inventors:
Mor Miller, Ariel Yagil, Itay Lusky, Liran Brecher, Amir Peleg, Naftali Sommer
Abstract: A method of communicating data across a channel that experiences near-end cross talk (NEXT) interference and far-end cross talk (FEXT) interference in alternate intervals. In one embodiment, a first data rate is determined for a first carrier-number mode that is to utilize a first bit table, a second data rate is determined for a second carrier-number mode that is to utilize dual bit tables, a third data rate is determined for a third carrier-number mode that is to utilize a second bit table during a FEXT interval, and a modem is configured to transmit using the mode having a highest data rate.
Type:
Grant
Filed:
June 25, 2008
Date of Patent:
June 8, 2010
Assignee:
Texas Instruments Incorporated
Inventors:
Konrad W. Kratochwil, Thomas N. Zogakis, Peter J. Melsa
Abstract: A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a probability value estimate and a check node value estimate, the probability value estimate and the check node value estimate associated with a parity check matrix. The system also comprises a plurality of parity check update modules (PCUMs) in parallel with each other, coupled to the first adder module and adapted to update the check node value estimate, and a second adder module coupled to the plurality of PCUMs and adapted to update the probability value estimate using the extrinsic estimate and the updated check node value estimate. The PCUMs process at least some columns of at least some rows of the parity check matrix in a serial fashion.
Abstract: A high-speed integer multiplier unit multiplying operands, wherein each operand can be either signed or unsigned. Type data is received for each operand which indicates whether the corresponding operand is to be treated as signed or unsigned. An extend bit is appended to each operand to provide extended operands, where the extend bit is the most significant bit of the corresponding operand if type data indicates that the operand is signed, and the extend bit is a logic zero otherwise. The extended operands are multiplied using a signed multiplication operation to provide the result. Overflow detection is done in parallel to the multiply operation, thus moving overflow-detection logic from the timing-critical path from the multiplier block's input to its output. The throughput performance of the multiplier unit is improved as a result.
Abstract: Systems and methods for efficient transmission of packets within a network communication device are described herein. Some illustrative embodiments include a network communication device that includes a plurality of ports (each port configured to communicate with one or more network devices), and a bus coupling the plurality of ports to each other (the bus providing a shared path for one or more bus transfers originated by a first port of the plurality of ports, and the one or more bus transfers including information). The bus includes a plurality of port map bits, a port map bit of said plurality of port map bits corresponding to a second port of the plurality of ports. The second port is configured to forward the information to the one or more network devices if the port map bit is asserted.
Abstract: A network infrastructure device includes a receiver operable to receive packets when operably connected to a communication network; and a processor cooperatively operable with the transceiver. The processor can receive a packet on an interface corresponding to the transceiver. Also, the processor can map the packet to one of several queues and to one of several classifications, based on an indication of priority of handling in a header in the packet and/or an indication of priority in a configuration of the interface. The processor also checks for congestion in the queues with respect to the classification of the packet, and checks for congestion in the one queue with respect to the one classification. The processor queues the packet if there is no congestion, otherwise the processor drops the packet.
Type:
Grant
Filed:
May 30, 2006
Date of Patent:
May 25, 2010
Assignee:
Texas Instruments Incorporated
Inventors:
Pankaj Kapoor, Fongchi Rex Chang, Jackie Lee Manbeck, Jr.
Abstract: In at least some embodiments, a system may comprise one or more devices configurable to communicate according to a first protocol that implements a first data packet, and one or more devices configurable to communicate according to a second protocol that implements a second data packet having a predetermined quadrature component. The one or more devices configurable to communicate according to the second protocol associate detection of the predetermined quadrature component with a function that is not supported by the one or more devices that communicate according to the first protocol.
Type:
Grant
Filed:
February 13, 2004
Date of Patent:
May 4, 2010
Assignee:
Texas Instruments Incorporated
Inventors:
Arndt Joseph Mueller, Karthik Ramasubramanian
Abstract: A system and method for providing a high voltage ultrasonic drive signal from an ultrasound transmitter are disclosed herein. An ultrasound transmitter includes a first plurality of drive transistors. A bias network is coupled to at least one transistor of the first plurality of drive transistors. A first switch is coupled to the bias network. The first switch selectively connects a first voltage to the bias network. The first switch is closed when generating an ultrasonic drive signal. The first switch is open when the transmitter is not generating an ultrasonic drive signal.
Abstract: A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/fT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency.
Type:
Grant
Filed:
September 18, 2007
Date of Patent:
April 20, 2010
Assignee:
Texas Instruments Incorporated
Inventors:
Nir Tal, Robert B. Staszewski, Ofer Friedman
Abstract: A method of tracing data processor activity includes trace data markers indicating initiation and termination of at least one trace function at a specified program counter address and emulation pause related markers indicating initiation and termination of an emulation halt state at a specified program counter. Each emulation pause related marker includes a conflict bit indicating the presence or absence of a simultaneous trace data marker having a different program counter address.
Abstract: An aspect of the present invention takes advantage of the fact that the coordinates of fixed points do not change, and thus the energy (sum of squares of the coordinates defining the vector) of each fixed point is computed and stored. The energy of each variable input point may also be computed. The distance between each pair of fixed and input points is computed based on the respective energies and the dot product.
Abstract: A method or device handles memory management faults in a device having a digital signal processor (“DSP”) and a microprocessor. The DSP includes a memory management unit (“DSP MMU”) to manage memory access by the DSP, and the DSP and the microprocessor access shared physical memory. Upon the DSP executing an instruction attempting to access a virtual address wherein the virtual address is invalid, a page fault interrupt is generated by the DSP MMU. A microprocessor interrupt handler in the microprocessor is activated in direct response to the page fault interrupt. Thereafter in the microprocessor, a translation lookaside buffer (“TLB”) entry is created in the DSP MMU, which includes a valid mapping between the virtual address and a page of physical memory. After creating the TLB entry, the microprocessor indicates to the DSP that the access by the DSP of the virtual address is completed.
Abstract: An arrangement avoids contention on a communication medium among devices including at least a transmitter and a receiver. The arrangement involves a first portion configured to instruct a receiver to indicate that the communication medium is busy for a time period substantially longer than an actual frame transmission period being sent from the transmitter to the receiver, and a second portion configured to prohibit the receiver from transmitting on the communication medium during the time period.
Abstract: A method for Orthogonal Frequency Division Multiplexing Access (OFDMA) ranging is provided. The method includes receiving a signal having OFDMA symbols. An FFT is performed on this signal. Matching ranging codes are found. The power for a given hypothesized ranging code is determined and compared to a power threshold to determine if the code was transmitted. The timing offset and power are reported as the result of ranging.
Abstract: Embodiments of the invention provide embodiments of the invention provide and method, network entity and user equipment for slow uplink power control of user equipment in a wireless communication system by responding to a long term control metric that is derived from an uplink channel metric over a plurality of transmission instances and a set of performance criteria. A method for slow uplink power control in accordance with and embodiment of the invention measures at least one uplink channel metric for user equipment and then determines an appropriate transmit power for the user equipment by using a control metric derived from the uplink channel metric corresponding to a plurality of transmission instances for the user equipment.
Type:
Grant
Filed:
June 20, 2006
Date of Patent:
February 23, 2010
Assignee:
Texas Instruments Incorporated
Inventors:
Eko N. Onggosanusi, Timothy A. Schmidl, Aris Papasakellariou, Anand Dabak