Abstract: A system and method for adaptively determining power cutback in communication system is described. According to an embodiment, the receiver determines noise on each sub-channel for different internal gain settings. It calculates what gain setting would be optimal from an SNR point of view and what power cutback value would lead to that gain setting.
Abstract: Each of a plurality of nodes in a wireless network is capable of generating, transmitting, and receiving beacons in a distribute fashion. Each beacon contains information regarding the order of which other nodes are to transmit beacons and wireless medium access information at to when various nodes are to access the network. Nodes that are in separate “extended neighborhoods” are permitted to transmit their beacons simultaneously without risking beacon collisions. The beacons contain information that is used to ensure this result. Using the distributed beacon mechanism, each nod can reserve access to the wireless medium. In the disclosed embodiments, a central coordinator is not needed.
Abstract: A system is provided that includes a first device 110A that transmits an information symbol with a zero-padded suffix (ZPS) and a second device 110B that receives the information symbol with the zero-padded suffix. The second device 110B performs a Fourier transform on at least one sample of the information symbol before a ZPS sample is overlapped-and-added to another sample of the information symbol.
Abstract: A low density parity check (LDPC) code for a belief propagation decoder circuit is disclosed. LDPC code is arranged as a macro matrix (H) representing block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix with a shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns are grouped, so that only one column in the group contributes to the parity check sum in a row. A parity check value estimate memory is arranged in banks logically connected in various data widths and depths. A parallel adder generates extrinsic estimates for generating new parity check value estimates that are forwarded to bit update circuits for updating of probability values. Parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.
Abstract: The present invention provides a post-channel estimate phase corrector for use with a multiple-input, multiple-output (MIMO) receiver employing M receive antennas, M being at least two. In one embodiment, the post-channel estimate phase corrector includes a pilot sequence coordinator configured to receive a pattern of pilot sequences from the M receive antennas during data symbol time periods. The post-channel estimate phase corrector also includes a phase calculator coupled to the pilot sequence coordinator and configured to calculate phase corrections for individual channel estimates based on the pattern of pilot sequences.
Abstract: Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is disclosed. Error correction coding according to a fixed-block size code, such as low density parity check (LDPC) coding, is implemented. The codeword length, and codeword arrangement, are selected by determining a minimum number of OFDM symbol periods required for a payload size, and the number of available information bits in those symbol periods. A rule-based approach, for example in a table, is used to select the codeword length, and the number of codewords required. Shortening is then applied to the code, followed by determining whether puncturing or repeating of bits is necessary to efficiently use the available OFDM symbols.
Abstract: System and method for synchronizing clocks and maintaining packet timing relationships in a wireless communications system. A preferred embodiment further comprises periodically synchronizing local clocks at a transmitter and a receiver to a clock reference, adding a timestamp to each application packet at a transmitter of a wireless network, setting the timestamp to a value of a local time at the transmitter plus a link delay, buffering a received packet at a receiver, and releasing the buffered packet to an application level when a value of a local time at the receiver equals the timestamp value in the packet. This can help to ensure that the timing relationships between data packets present at a transmitter is maintained at a receiver, regardless of transport delays (waiting, transmission and processing) incurred by the data packets.
Type:
Grant
Filed:
May 18, 2004
Date of Patent:
February 23, 2010
Assignee:
Texas Instruments Incorporated
Inventors:
Jin-Meng Ho, Richard T. Baker, Allison Winifred Hicks
Abstract: Embodiments of the invention provide a versatile system for selectively spreading carrier data across multiple carrier paths within an Orthogonal Frequency Division Multiplexing (OFDM) system, particularly an ultra-wideband (UWB) system. The present invention provides a data input, which passes data to a randomizer. The data then passes to a convolutional code function (206), the output of which is punctured by puncturing function. An interleaver function receives the punctured code data, and cooperatively operates with a mapper element to prepare the coded data for pre-transmission conversion by an IFFT. The mapper element comprises a dual carrier modulation function, which associates and transforms two punctured code data elements into a format for transmission on two separate signal tones.
Abstract: A method of wirelessly communicating is disclosed. The method comprises determining a matrix W based in part on limiting a plurality of active interference cancellation tone values (416), determining the active interference cancellation tone values (416) based on W and based on a plurality of information data values (410), and transmitting an orthogonal frequency division multiplex signal (310) based on the plurality of active interference cancellation tone values (416) and the information data values (410).
Abstract: Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is disclosed. Error correction coding according to a fixed-block size code, such as low density parity check (LDPC) coding, is implemented. A specific LDPC code with excellent error rate performance is disclosed.
Abstract: In at least some embodiments, a system may comprise one or more devices configurable to communicate according to a first protocol that permits interpretation of transmitted symbols associated with a first time duration. The system may further comprise one or more devices configurable to communicate according to a second protocol that permits interpretation of transmitted symbols associated with multiple time durations. The one or more devices configurable to communicate according to the second protocol are operable to communicate using transmitted symbols associated with the first time duration and to communicate using transmitted symbols associated with a time duration that is not supported by the one or more devices configured to communicate according to the first protocol.
Type:
Grant
Filed:
June 17, 2004
Date of Patent:
February 23, 2010
Assignee:
Texas Instruments Incorporated
Inventors:
Markos G. Troulis, Arndt Joseph Mueller, Karl E. Fitzke
Abstract: The present application describes a method and system for discovering and authenticating communication devices within a wireless network. According to an embodiment, communication devices exchange public keys using multiple messages each including at least a portion of the public key of the sending device. The devices authenticate the receipt of the public key and establish a shared master key. The shared master key is used to further derive a session key for securing the application data between the communicating devices for a current session.
Abstract: Embodiments of the invention provide method and apparatus for generating a structure in an orthogonal frequency division multiplexing OFDM communication system having a transmitter with one or more transmitting antennas. The method includes composing a frame with a time domain and a frequency domain. The frame has a transmission time interval in the time domain and occupies a bandwidth in the frequency domain. The transmission time interval has multiple orthogonal frequency division multiplexing symbols. A pilot signal is located from a transmitting antenna into two non-consecutive orthogonal frequency division multiplexing symbols of the frame.
Type:
Grant
Filed:
June 19, 2006
Date of Patent:
February 9, 2010
Assignee:
Texas Instruments Incorporated
Inventors:
Aris Papasakellariou, Timothy A Schmidl, Eko N Onggosanusi, Anand Dabak
Abstract: A system and method for improving bit-loading in discrete multitone (DMT)-based digital subscriber line (DSL) modems. In one embodiment, the system includes: (1) a model generator configured to generate a model containing a calculated total bit loading for an assumed gross coding gain and estimated total bit loadings for a other plurality of assumed gross coding gains and (2) a bit loader associated with the model generator and configured to load bits in accordance with the model.
Abstract: A method is provided for dramatically improving communications data throughput on embedded systems and reducing the load on the operating system and central processing unit by moving the network protocol logic nearer to the underlying communication hardware, and utilizing the communication processor hardware abstraction layer (CPHAL) concepts. This movement of the network protocol logic allows leveraging the CPHAL data structures, which are tightly bound to the communication packets being processed. The decision making is made just above the CPHAL layer; and the CPHAL data structure is preserved. Copying data is avoided by manipulating of pointers within the CPHAL buffer.
Abstract: In a method, system and apparatus for measuring an idle value of a Central Processing Unit (CPU) in an embedded system, the CPU increments a hardware counter in accordance with clock signals. The CPU also increments an idle counter during a predetermined period of time in accordance with the clock signals while an idle task is running. The CPU calculates the idle value as a ratio of total increments of the idle counter to total increments of the hardware counter after the predetermined period of time has expired.
Abstract: Methods and apparatus for power monitoring with sequencing and supervision are disclosed. An example method disclosed herein includes supervising a first power rail and a second power rail, sequencing a first enable signal associated with the first power rail and a second enable signal associated with the second power rail, and determining whether the first power rail is enabled based on regulation information determined while supervising the first power rail.
Type:
Grant
Filed:
March 30, 2007
Date of Patent:
December 8, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
David Allan Comisky, Brandon Christopher Azbell, Bradley James Griffis
Abstract: One embodiment of the present invention includes a communication system. The system comprises a communications controller configured to control transmission and reception of communications data in a network. The system also comprises a memory configured to store configuration data associated with the communications controller and application parameters associated with each of a plurality of communications applications. The system further comprises an interface converter interconnecting the communications controller and the memory and configured to convert a first bus interface protocol associated with the communications controller to a second bus interface protocol for providing read and write data transfer of the configuration data and the application parameters between the communications controller and the memory.
Abstract: A method to reduce memory requirements for a packet loss concealment algorithm in the event of packet loss in a receiver of pulse code modulated voice signals. A voice playout unit in the receiver shares its nominal delay buffer with a history buffer of a packet loss concealment algorithm up to a maximum limit described in a standard. This reduces or eliminates need to allocate memory for the history buffer. A history buffer can also be extended to retain an original portion of voice signal packets received prior to a packet loss as well as generated voice signals as they are generated. A scratch buffer is used as a working buffer and replaces the function of a pitch buffer.
Type:
Grant
Filed:
February 14, 2005
Date of Patent:
September 15, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
John T. Dowdal, Sachin Adlakha, Dunling Li
Abstract: A procedure for accomplishing surveillance within a managed VoP network when end-user encryption/decryption and NAT are in place. The procedure comprises first analyzing the network from call signaling and message standpoints, leading to the identification of suitable surveillance access points (SAPs) for packet interception. A Delivery Function (DF) facilitated by the network service provider provides the means to intercept (without alteration) and replicate packets transmitted across the SAPs. The packets are then transmitted via the DF for collection within a Collection Function (CF), which is managed by a Law Enforcement Agency (LEA), for analysis by the LEA. This analysis provides, among other benefits, the opportunity to decrypt the intercepted packets and to identify additional suitable SAPs. In demonstrating the procedure, several embodiments of network surveillance models are described. Each one identifies the location of SAPs for that model.
Type:
Grant
Filed:
February 10, 2005
Date of Patent:
September 8, 2009
Assignee:
Texas Instruments Incorporated
Inventors:
Shwu-Yan Chang Scoggins, Debbie E. Greenstreet