Abstract: An apparatus and method for stereoscopic 3D image projection and viewing using a single projection source, alternating polarization, and passive eyewear. This approach is applicable to frame sequential video created using existing 3D graphics APIs, as well as other video signal formats, and is compatible with existing digital light processor (DLP) technology for both front and rear projection systems. An alternating polarizer in the form of a magnetomechanically resonant polarizing filter actuator is used to modulate the projected image. A preferred embodiment enables an existing DLP projection system to be enhanced with 3D capability.

Abstract: In a stereographic projector that places a single linear polarizing wheel in the light path of the projector to impart a desired polarization state onto the projected light, a method and apparatus for periodically slowing the wheel down while in optimal states, and accelerating through invalid states. Stereo separation is greatly increased providing a marked improvement in visual quality and perceived depth when this invention is applied to such a polarizing filter wheel.

Abstract: A 3D stereographic projection apparatus comprises an input for receiving stereographic image data that includes sync signals corresponding to image streams in the image data. A digital light projector projects the stereographic image data. A motor driven rotating filter has a marker disposed thereon positioned in the path of the projected stereographic image data. The motor driven rotating filter separately polarizes the image streams in the stereographic image data. A motor drive circuit, coupled to the input, receives the sync signals and synchronizes a rotation of the filter with the sync signals. A tach sensor, comprising a light transmitter and detector coupled to the rotating filter, detects the marker and outputs marker signals indicating that the marker is detected.

Abstract: Techniques for accounting microprocessor resource consumption. The present invention provides an automatic method to timely determine the current microprocessor clock frequency. Information provided by timer facilities of the microprocessor is reused by sampling this information at constant intervals. Such direct derivation of the microprocessor clock frequency is a real-time method that also takes into consideration secondary effects. Examples for such secondary effects include clock frequency variations across chips due to manufacturing variations, any degradation due to performance loss by thermal, or other detrimental effects as well as any voltage changes. In the preferred embodiment of the invention, the real-time microprocessor clock frequency determination is implemented as part of the microprocessor itself. No additional service processors or other external hardware facilities are needed in order to control the microprocessor clock frequency determination function.

Abstract: The idea of the present invention is to provide a challenge-response mechanism to acquire work scope split range information from the application's Work Scope Split component of the over-utilized resource. By using the work scope split range information, the provisioning system is able to add a new resource, install a new application for that new resource, configure the new and the over-utilized resource's application, and reconfigure the load-balancer in accordance with the work scope split range information. The present invention adds scalability to complex and stateful application programs and allows dynamic provisioning of resources for these application programs.

Abstract: Injection molding of monolithically integrated optical components is disclosed. In one embodiment, an injection molding system includes a moldplate having an array of specially designed cavities. In at least one cavity, different types of photo-curable optical materials are injected in an ordered sequence. In a first instance, a lens material is injected into the cavity and subsequently cured to form a predetermined lens element at the base of the cavity. In a second instance, a filter material is injected into the cavity above the already formed lens element. The filter material is also cured, and an optical filter is formed stacked onto the lens element and contained within sidewall of the cavity. In this manner, a complex optical component having an optical filter automatically aligned with, and monolithically integrated into, a lens element is readily formed in a single injection molding process.

Abstract: A method for manufacturing an organic electronic device including a stack of layers including a release layer, the stack having a lateral structure on a substrate, at least one of the layers being an organic material layer. A method includes with the step of providing a stamp with at least one protrusion of the surface area corresponding to the lateral structure. The stack of layers is deposited with a first face on the surface area of the protrusion of the stamp. A second face of the stack that is opposite to the first face is brought into adhesive contact with the substrate. The stamp is released from the stack.

Abstract: Creating a unique identification for each stack in partitions of a host data computer such that a plurality of partitions may share a single adapter card during an Input/Output operation wherein the adapter card is exchanging data between the host and a Local Area Network. The adapter card includes a unique identifier pool for maintaining values of unique identifiers which are available for identifying the stacks. A deleted unique identifier for a stack may be reused by newly created stacks and may be reassigned to a recreated stack, if still available, when the stack had previously been deleted by the operating system, but is then recreated.

Abstract: The present invention relates to methods and apparatus for producing an electronic device, such as an organic light-emitting diode (OLED), having an electrode with enhanced injection properties. An example method according to the invention comprises the steps of providing an electrode, depositing a first layer of molecular charge transfer material on the electrode, and cross-linking the molecular charge transfer material. With the method according to the invention, an OLED with higher light efficiency, lower operating voltage, and longer lifetime can be produced. The present invention further relates to an electronic device having an electrode with enhanced injection properties.

Abstract: The invention relates to a delay calculation method for wiring nets of an electronic circuit, wherein a net within an electronic circuit comprises a driver pin and a receiving pin being coupled by at least one loop, the loop comprising a first branching path and a second branching path electrically parallel to the first branching path, wherein at least a first and a second branching point connect the branching paths. The method comprises the steps of disconnecting each branching path once at a time at a specific point in said the at least one loop which connects a driver to at least one specific receiving pin; calculating a delay value of a signal connection between the driver pin and each of the receiving pin for each of the disconnected branching paths of each loop; storing maximum and/or minimum calculated delay values; and applying at least one of the delay values for static timing analysis of the electronic circuit.

Abstract: Controlling an unreliable data transfer in a data channel from a transmitting unit to a receiving unit. A bypass mode or a buffer mode is activated depending on the error rate in the data channel. If bypass mode is selected, data packets are directly transferred in probation from the transmitting unit to the receiving unit by a bypass line. The data packets are error checked after the data transfer. If buffer mode is selected, data is transfer from the transmitting unit to the receiving unit by a buffer line via an error detecting and correcting unit and a buffer unit. The errors are detected and corrected during the data transfer.

Abstract: A new multi nodal computer system comprising a number of nodes on which chips of different types reside. The new multi nodal computer system is characterized in that there is one clock chip per node, each clock chip controlling only the chips residing on that node said chips being appropriate for sending a check stop request to the associated clock chip in case of a malfunction. A new check stop handling method is characterized in that depending on the source of the check stop request the clock chip that received the check stop request initiates a system check stop, a node check up, or a chip check stop.

Abstract: Techniques for replicating modified data to a hierarchical database. A first list comprises records included in a set of records before at least one modification thereto. A second list comprises records included in the set of records after the at least one modification thereto. For each pre-modification record included in the first list and each post-modification record included in the second list having equal identifying values, a target record at the database and having a matching identifying value is modified. Specifically, if both records include corresponding indexes, information about a structure pointed to by the pre-modification record is removed from an index included in the target record, and information about a structure pointed to by the post-modification record is added to the index. If neither record includes an index, the target record is modified to contain at least one changed value included in the post-modification record.

Abstract: An integrated optical I/O and semiconductor chip with a direct liquid jet impingement cooling assembly are disclosed. Contrary to other solutions for packaging an optical I/O with a semiconductor die, this assembly makes use of a metal clad fiber, e.g. copper, which will actually enhance cooling performance rather than create a design restriction that has the potential to limit cooling capability.

Abstract: An Infiniband flow control scheme disables credit based flow control so that transmission distances can be extended. An Infiniband credit based flow control suffers from round trip time lag that slows transmission rates. Disabling Infiniband credit based flow control enables back to back packet transmission because credit counts are ignored. Nonetheless, packets can be lost due to overruns in a receive buffer, therefore, packet drop detection mechanisms are employed so that the Infiniband receiver can send requests to the Infiniband transmitter to temporarily slow its Infiniband transmission rate.

Abstract: A low latency multicasting receive and send apparatus and method comprising low latency receive and send queues. In an InfiniBand® network each destination group of nodes (recipients) is identified by a unique Global ID (GID)+Local ID (LID). Each node whose ports are part of a multicast group identify themselves via a LID which identifies participating ports. When a switch receives such a multicast packet with a multicast LID in the packet's DLID field it replicates the packet to each of the designated ports. Each destination adapter at a receiving node receives the multicast packet and distributes copies of the packet to QPs in the host system that are registered for the multicast address.

Abstract: An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.

Abstract: A system and process for passing messages directly between instances of Operating System (OSs) and plurality of Coupling Facilities (CFs) through Sharable InterSystem Channels (ISCs) and without polling, in one or more Computer Electronic Complexes (CECs). Primary messages and associated secondary messages are passed by a hypervisor using a hypervisor memory.

Abstract: Communication over a computer network with a node having a first port with a point-to-point link connection to a second node having a second port. The first port transmits to the second port a reliable link layer (RLL) packet over the link. The RLL packet comprises a first RLL header and a first data packet, the first RLL header preceding the first data packet, the first RLL header comprising an RLL start-of-frame (SOF) character and an RLL packet sequence number (PSN). If the first port receives an RLL acknowledgment control packet from the link, it acknowledges receipt of the first data packet, and the first port does not retain the first data packet in the buffer. If the first port does not receive the RLL acknowledgment packet from the link, acknowledging receipt of the first data packet, the first port re-transmits from the buffer the first data packet.

Abstract: The invention proposes a Floating Point Unit with fused multiply-add, with one addend Method for calculating a result of a division with an A-register and a B-register for two multiplicand operands and a C-register for an addend operand, wherein a divide processor using a subtractive method for calculation with a divisor register and a partial remainder register and a multiplier associated to an subtractor uses the C-register as input, wherein while loading the fraction of the dividend through the divisor register into the partial remainder register of the divide processor a calculated shifting is applied for alignment by using the multiplier associated to the subtractor.