Abstract: A novel serial data communication interface architecture is provided having two modes of operation that are accessed through a chip select signal in combination with a successive approximation registers signal (SARS). Once the internal data conversion begins, the chip select signal may change to any signal state without interrupting the conversion process. Serial interface data output and SARS lines are tri-stated during conversion, while the chip select signal is high. This allows data input, data output, and SARS lines to serve other purposes during conversion. If chip select signal is high at the falling edge of SARS, converted data DO bits are then provided to an internal output register. However, DO data are not immediately routed to the output. Clocking of the output data does not resume until at the first transition to low of chip select signal after the falling edge of SARS.

Abstract: A novel row decoder/driver circuit in which switched bias voltages are applied to the bulk regions in order to minimize the maximum voltage differential appearing across transistor devices. This allows the decoder/driver circuit to be conveniently fabricated and designed to allow normal transistors rather than more complex and expensive high voltage transistors, to form the row decoder/driver. The bulk regions containing the pull-up and pull-down transistors are biased by voltages which are switched during erasure depending on whether the row line is selected or deselected in order to assure that excessive voltages do not appear across based upon the voltage levels applied to the transistors.

Abstract: A method for preprocessing reference feature vectors representing patterns in order to form, for each selected pattern class, collections of regions. A hierarchy of possibility regions is formed, wherein all reference feature vectors of a pattern class are contained in each level of the hierarchy of possibility regions associated with the pattern class. This hierarchy is later used to exclude a pattern class from consideration if a feature vector representing an unknown pattern is not contained in some level of its associated hierarchy of possibility regions. A collection of certainty regions is used, wherein no reference feature vector not of a pattern class is contained within any certainty region associated with the pattern class. The certainty regions are later used to classify a feature vector representing an unknown pattern as belonging to a pattern class.

Abstract: Improved integration and simplified construction of direct conversion receivers is achieved by providing selectivity in the early stages of a sigma delta converter to reject adjacent channel signals and thereby allow greater dynamic range for the desired input signals. A bandpass sigma delta converter is taught which is suitable for use with signals having multiple protocols. In a first stage, an aliased input signal is applied to two filters having desired and preferably programmable filter characteristics which provide selectivity to the input signal. A third filter is utilized having a programmable center frequency, which receives as an input signal the sum of the filtered input signal plus the quantization noise of the first stage. This provides a first intermediate output signal of desired selectivity.

Abstract: A PLL frequency synthesizer utilizes circuitry for altering pump current magnitude based upon division factors in the PLL. In one embodiment, pump current magnitude is responsive to the feedback division factor path, providing a constant gain over a wide frequency range, thereby providing a constant natural frequency and damping. In another embodiment, pump current magnitude is controlled as a function of both feedback and feedforward division factors, thereby maintaining a constant natural frequency with respect to the output frequency. In another embodiment, the output frequency is proportional to the VCO control signal raised to a power, with charge pump current controlled as a function of the feedforward division factor thus providing a natural frequency and damping factor which is constant with respect to output frequency. In another embodiment, gain control is provided as a function of at least one division factor in a PLL loop which does not utilize a charge pump.

Abstract: A dynamic RAM is provided with enhanced charge storage capacity by increasing the surface area between the two electrodes of the storage capacitor. The first electrode consists of a thick conductive layer whose vertical sidewalls provide the extra surface area for charge storage. The second electrode is used to partially planarize the surface topology. The first electrode can also be used as the gate of a sensing transistor in a signal amplifying cell, as well as in multiport and multistate dynamic RAM cells.

Abstract: A computer data storage device made up of both solid state storage and rotating magnetic disk storage maintains a fast response time approaching that of a solid state device for many workloads and improves on the response time of a normal magnetic disk for practically all workloads. The high performance is accomplished by a special hardware configuration coupled with unique procedures and algorithms for placing and maintaining data in the most appropriate media based on actual and projected activity. The system management features a completely searchless method (no table searches) for determining the location of data within and between the two devices. Sufficient solid state memory capacity is incorporated to permit retention of useful, active data, as well as to permit prefetching of data into the solid state storage when the probabilities favor such action.

Abstract: An end user query technology is taught which is capable of automatically understanding the database model and guiding the user to scout for the desired information, thereby increasing productivity and ease of information access. The user is freed from the need to understanding the database model, with the end user query facility of this invention quickly guiding the user to acquire the information. This is made possible by the end user query facility of this invention first recapturing the application semantics from the existing database model to provide a set of derived semantics. The derived semantics are then used by the end user query facility to intelligently guide the user to scout for the desired information in the database. In addition, the derived semantics can be easily updated by the end user query facility when the database model is changed.

Abstract: This invention is a novel document preparation system in which a user is capable of viewing various permutations of a predefined portion of text. With this invention the display of variations in text is performed automatically. This provides a technique by which the developer can more quickly audit the results of his work and on the user's side it permits the user to rapidly see a wide variety of different transactions which is of enormous use to a young associate learning a particular practice area. In one embodiment, the user is provided with a subset of the total number of permutations of a particular portion of text. Various techniques are used to provide only "meaningful" variations of the text, thereby avoiding the need for the user to view what might be an extremely large number of permutations, many of which are of no real import based upon the task at hand.

Abstract: An input stage suitable for use with any desired supply voltage VCC, including supply voltages less than 5 volts, and which is capable of withstanding an overvoltage input signal greater than VCC applied to its input pad. A pass transistor is used between the input pad and the input buffer in order to limit the voltage supplied to the input buffer, thereby allowing voltages in excess of VCC to serve as a legitimate logical one input signal to the input buffer. Overvoltage protection is used to limit the voltage on the input pad to a voltage in excess of the greater-than-VCC legitimate input voltage. An output stage is suitable for use with a wide variety of supply voltages, including supply voltages less than 5 volts, while allowing proper operation in the event that a legitimate overvoltage is applied to its output pad. ESD protection is provided in order to limit the voltage on the output pad to a voltage greater than the maximum legitimate overvoltage.

Abstract: A semiconductor fabrication process is provided which prevents the cratering of the bond pads of an integrated circuit by including in a semiconductor process an etch stop layer which is formed between the field oxide layer and the first dielectric layer to prevent erosion of the field oxide while allowing etching and removal of the first dielectric layer to prevent cratering.

Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation.

Abstract: An improved current source having high output impedance, low saturation voltage, and less sensitivity to process parameters is achieved by having enhancement P-channel transistor devices used as current mirror, while depletion P-channel transistor devices are provided as the cascode devices. A "diode connected" depletion device may be inserted between the enhancement gate and the drain of the current reference transistor to reduce saturation voltage. The "diode connected" depletion device keeps the drains of the enhancement devices at a similar voltage even when the enhancement and depletion device threshold, i.e. V.sub.T, do not track over temperature or process. Thus, the current mirror circuit provides not only higher output impedance, lower saturation voltage, but is also less sensitive to process variation.

Abstract: An object-oriented technology is provided which is capable of operating interpretively to allow prompt and easy prototyping and debugging using a compiled class library, and which is also capable of operating after compilation, thereby providing excellent performance. A software facility allows direct access to class attributes and direct invocation of class methods defined in pre-compiled classes in a class library in an interpretive mode. When this facility is used with or embedded within an application development environment, it allows an application builder to interactively build prototypes as well as production quality applications rapidly. When the facility is integrated with an object-oriented database, it allows interactive query and data manipulation using pre-complied classes.

Abstract: A method is provided for use with an Ethernet Media Access Controller (MAC) and a look-up memory external to the MAC, the method determines whether to accept or to reject an Ethernet packet which is decoded by the MAC into a serial data (SRD) signal stream and a serial data clock (SRDCLK) signal, the method comprises the steps of: converting the SRD signal stream into byte frames and loading the frames into a receive FIFO of the MAC; while the receive FIFO is being loaded, producing by the MAC, a boundary delimiter (BD) signal stream which delimits the frame boundary of each byte frame; while the receive FIFO is being loaded, providing the SRD signal stream, the SRDCLK signal and the BD signal stream from the MAC to the look-up memory; while the receive FIFO is being loaded, determining whether a prescribed field in the packet matches information stored in the look-up memory; while the receive FIFO is being loaded, informing the MAC by the look-up memory whether a match has been detected.

Abstract: A novel nonvolatile memory cell structure is provided using a non-self aligned CMOS process with two independent N+ implants using a two or a three polysilicon layer technology that allows in-circuit electrical erase and reprogramming together with reduction in cell size requirement. The novel memory cell is implemented with a merged transistor structure having an access transistor and a programmable transistor. The memory cell is constructed by having the control gate, formed of a first polysilicon layer, covering a portion of the channel length between drain and source to form the access portion of the merged transistors, and a floating gate formed of a second polysilicon layer overlapping a second portion of the channel length to form the programmable transistor portion of the merged transistor. Such merged transistor structure is equivalent to two transistors in series, a programmable transistor in series with an access transistor.

Abstract: A byte tracking system (60) has a 32-bit wide system data bus (34). System bus interface unit (48) connects the system bus (34) to the transmit FIFO buffer memory (42) to supply 4-byte data words (62) to the FIFO buffer memory (42). The FIFO buffer memory (42) has word write and read accessibility. A 4:1 multiplexer (64) is connected at the output side of the FIFO buffer memory (42) by a 32-bit wide bus (66). The multiplexer (64) is used to multiplex correct bytes (63) from the data words (62) to an 8-bit output bus (68). A byte tracker circuit (70) controls the multiplexer (64) and determines which byte (63) is to be sent to the output bus (68). The bytes (63) supplied to output bus (68) are converted by a parallel to serial converter (69) to a serial bit stream, which is supplied to Manchester encoder/decoder (36).

Abstract: An electronic video dental camera is provided which overcomes the disadvantages of both prior art dental mirrors, endoscopes, and video endoscopes. The electronic video dental camera is readily manipulated by dentists who are familiar with the manipulation of dental mirrors. Such an electronic video dental camera includes a handle to be held the user, and a camera head located at the distal end of the handle, with the camera head being formed at an angle to the handle, as in prior art dental mirrors. One embodiment includes provision for the flow of a selected fluid in order to defog and/or clean the camera lens. In one embodiment, the camera head includes light sources for illuminating the area to be viewed. In one embodiment, the handle of the dental camera includes means for transporting all appropriate signals and fluids to and from the camera head, and, if desired, valves and switching means located on the handle for controlling such communication to the camera head.

Abstract: This invention teaches new types of linearization circuits, exhibiting improved broadband suppression of nonlinear distortion. These realizations do not require the use of reactive elements such as capacitors, or of active elements such as transistors, eliminating the drawbacks of prior art realizations. The linearization circuits are particularly suitable for linearizing optical sources with odd wave voltage to light transfer characteristics, such as externally modulated CW lasers. The fundamental building blocks of the linearization circuits of this invention are novel nonlinear electrical one-ports with an expansive V-I characteristic, denoted as ENLOP (Expansive Nonlinear one-Ports). The ENLOP building blocks are further embedded in linear circuits.

Abstract: An EPROM register is programmed in a manner substantially similar to the manner used to program a main EPROM array contained on the same integrated circuit. Data in the main EPROM array must be read out by applying appropriate address and output enable signals. The EPROM register allows the data stored therein to be available at all times by providing a full-time static output signal. The register includes a static evaluation circuit for determining the data stored in the register, a precharge keeper circuit for providing a pseudo-static evaluation of the data, as well as providing a periodic refresh of the sense node during pseudo-static evaluation, and a margin test circuit for testing the threshold voltage of the register, as well as actual or relative shifts in the threshold voltage. The EPROM register serves as a nonvolatile memory which can be written to store configuration information for an integrated circuit.