Abstract: A process is taught which provides very shallow conductive regions in a semiconductor material by the formation of a fixed charge placed in an overlying dielectric layer which induces an inversion region in the underlying semiconductor. The inversion region so formed is used as a MOSFET drain extension between a drain contact region and the channel located beneath the gate region. The conductivity of the induced inversion region is controlled by the concentration of the ionic charge present in the dielectric layer.

Abstract: A method and structure for forming in an EEPROM memory transistor a tunnel dielectric region having an extremely small surface area. A floating gate region is formed in the conventional manner above a gate dielectric layer. The drain region is exposed utilizing photolithographic techniques and the gate dielectric removed therefrom. A thin layer of tunnel dielectric is then formed on the exposed drain region. A thin layer of polycrystalline silicon is then formed and etched in order to create very narrow floating gate extensions of polycrystalline silicon along the edge of the previously formed floating gate. The floating gate extension formed in this manner which overlies the drain region is separated from the drain region by thin tunnel dielectric. A dielectric is then formed on the device in order to provide a dielectric over the drain region which has a greater thickness than the tunnel dielectric underlying the floating gate extension.

Abstract: A technique for operating a common emitter circuit from a plurality of supply voltages. In one embodiment, a current mirror includes a plurality of diode-connected transistors each connected between a source of current and associated supply voltages. Corresponding current mirrors are each connected between an output terminal associated supply voltage leads, thereby providing an output current mirrored from the soure of current, regardless of which of the supply voltages are activated, and regardless of their particular levels. In another embodiment, a regulator includes an output transistor having a plurality of current handling terminals, each connected to an associated supply voltage, and a second current handling terminal coupled to an output terminal.

Abstract: An output buffer circuit advantageously uses a simple integrated circuit package including two separate ground leads for connection to an externally supplied ground voltage. The relatively large pull down current which passes through the pull down transistor of one or more output buffers are fed through a first ground lead of the lead frame to the external ground and the remaining circuitry is connected to the external ground through the second ground lead of the lead frame. The transients in the pull down current will cause ground bounce which affects the pull down transistor only, and not the remaining components of the output buffer. In this manner, base drive to the output pull down transistor is not decreased due to ground bounce, and the high to low transition of the output voltage is not degraded by the presence of ground bounce. In an alternative embodiment, the amount of ground bounce is controlled to provide a desired characteristic of the output transition.

Abstract: A semiconductor fabrication process uses an epitaxial layer as an etch stop in a plasma etch process. In one embodiment, mechanical stops and an epitaxial layer are used in combination for stopping precisely at a desired end point.

Abstract: A PLA is formed using configurable logic elements. A plurality of pages are used to store information defining logic configuration patterns required to perform desired logical functions. The configurable logic elements are configured by downloading information from a desired one or more of said pages. If desired, page control is achieved in response to input signals to the configurable logic array.

Abstract: A method for preprocessing reference feature vectors representing patterns in order to form, for each selected pattern class, collections of regions. A hierarchy of possibility regions is formed, wherein all reference feature vectors of a pattern class are contained in each level of the hierarchy of possibility regions associated with the pattern class. This hierarchy is later used to exclude a pattern class from consideration if a feature vector representing an unknown pattern is not contained in some level of its associated hierarchy of possibility regions. A collection of certainty regions is used, wherein no reference feature vector not of a pattern classis contained within any certainty region associated with the pattern class. The certainty regions are later used to classify a feature vector representing an unknown pattern as belonging to a pattern class.

Abstract: A Safe Operating Area (SOA) circuit is constructed including a synthetic large value resistor that is an active current source whose output current is related to the power supply voltage, and whose absolute value may be arbitrarily low. A piece-wise current source is provided which includes means for generating one or more control voltages in order to control the level of output current in response to the input voltage. In one embodiment, each of the control signal means includes feedback means and a summing node, so that one or more functions are performed using a control signal as an input, with the result fed back to the summing node. In this manner, a complex function can easily be provided for controlling the magnitude of the output current. In one embodiment, the one or more control signals are provided by one or more saturating current mirrors in order to limit the output current made available.

Abstract: A method for classifying an input feature vector representing an unknown pattern as belonging to one of a set of pre-defined pattern classes, wherein the input feature vector is compared with pre-constructed regions. A hierarchy of possibility regions is used to exclude a pattern class from consideration. Certainty regions are used to classify with certainty the input feature vector as belonging to some pattern class. Confidence regions are used to identify, although not with certainty, the unknown input pattern and assign a confidence value indicating the relative confidence associated with the possiblity that this unknown pattern belongs to given pattern class.

Abstract: An encryption method is taught which chooses certain bytes of data, stored in a particular on-chip memory, as encryption keys. These chosen bytes are used to encrypt themselves, and all of the remaining data in the above mentioned particular memory. The chosen bytes do not have values specifically assigned for encryption, they are merely chosen, according to a rule, from the body of data to be encrypted. When this technique is implemented, each byte of data, stored in the mentioned memory, is combined (for example using an exclusive NOR gate) with one of the designated encryption key bytes prior to disclosure. The user is not required to provide, program, or safeguard a set of key bytes separately. Additionally, no silicon area is wasted in storing such bytes. An intruder would need certain pieces of the original data in order to decipher the results of this encryption technique. Additionally, this technique degrades gracefully.

Abstract: A cutter link for a chain saw chain containing a conical raker spaced forward of a round cutter face. The raker protects most of the cutter face from sudden impact and, together with the cutting and rake angles of the cutter face, provides for a filing rather than a chiseling action by the cutter link. Saw chains incorporating the novel cutter link are impact and wear resistant.

Abstract: A programmable logic device is constructed having a novel architecture. A plurality of control input signals are applied to a programmable mapping array in order to generate control functions for data path gating, latching, or modification. The programmable control functions provide flexibility to the designer, while the fixed data path logic is independent of the programmable array. The logic array and data path logic are fabricated on the same integrated circuit, therefore obviating the need for input/output buffers which would be necessary if the device were constructed utilizing discrete components. This enhances the performances of the device. Since the data path does not travel through the array, its performance is not affected by the programmability. If desired, the programmable array can be formed of mask programmable devices, fused programmable devices, or register based circuitry, for example, using RAM cells.

Abstract: A novel dental instrument is taught which includes both a laser device and an electronic video dental camera. The teachings of this invention overcome the disadvantages of prior art dental laser instruments which do not provide for other than direct viewing of the treatment area by the dentist, as well as the disadvantages of attempting to use such prior art dental laser instruments together with typical prior art viewing devices such as dental mirrors and dental cameras of the prior art. The dental instrument includes a laser device and an electronic video dental camera is provided having a single handle and a convenient shape, thereby being readily manipulated by dentists who are universally familiar with the manipulation of prior art dental tools.

Abstract: A method and structure is provided which allows for a plurality of patterns or characters which are joined to be separated for further processing. For characters which are determined not to have a fixed pitch, a first approximation cleavage point is determined based on the width of the segment. Next, a caliper histogram is formed plotting the distance between the uppermost and bottommost "on" pixel in each column of the segment. If a satisfactory minimum in the caliper histogram is found, this segment is cleaved into left and right segments at this point. It not, a raw histogram, indicating the total number of "on" pixels in each column of the segment, is formed. If an adequate minimum of the raw histogram is found, the segment is cleaved into right and left segments at this point. In one embodiment of this invention, the caliper histogram operation is not performed if it is determined that the segment includes top and bottom serifs.

Abstract: An integrated circuit package includes a plurality of TAB assemblies, each including a portion for inner lead bonding an integrated circuit. A portion of the tape is formed to allow the tape to be outer lead bonded to the substrate so that the integrated circuit is mounted at any desired non zero angle with respect to a horizontal substrate. A plurality of formed tape units are outer lead bonded to a horizontal substrate. In one embodiment, the die is inner lead bonded to the tape in an area which is not devoid of tape, allowing electrical traces on the tape which are routed above and not in contact with the surface of the die, thereby providing excellent routing density. The dielectric tape may include a single electrical interconnect layer, or a plurality of electrical interconnect layers which may themselves be electrically interconnected via suitable vias formed within the tape structure.

Abstract: In accordance with teachings of this invention a novel sense amplifier is provided. The sense amplifier includes an enable circuit which receives an enable input signal. This enable circuit includes a constant current source which consumes a small amount of power. The enable circuit provides an output signal which serves to disable the output pull up and pull down transistors of the sense amplifier, thereby providing a high impedance output signal. At the same time, the disabling output signal from the enable circuitry powders down the read circuitry, thereby minimizing power consumption.

Abstract: A PLA is formed using configurable logic elements. A plurality of pages are used to store information defining logic configuration patterns required to perform desired logical functions. The configurable logic elements are configured by downloading information from a desired one or more of said pages. If desired, page control is achieved in response to input signals to the configurable logic array.

Abstract: A novel method and structure is taught for synchronizing a received digital data stream to the receiver clock. A plurality of delay lines; are used to provide a plurality of delayed input signals, which are then compared with the receiver clock signal in order to determine which of the delayed input signals is closest in phase to the receiver clock signal. Once this determination is made, a multiplexer is used to select the appropriate one of the plurality of delayed input signals for use by the receiver. In an alternative embodiment, a plurality of delay lines are used to provide a plurality of delayed clock signals, which are then compared with the receiver input signal in order to determine which of the delayed clock signals is closest in phase to the receiver input signal. Once this determination is made, a multiplexer is used to select the appropriate one of the plurality of delayed clock signals for use by the receiver.

Abstract: A unique current sense means is provided in which a bonding wire or similar conductor is routed to one or more Hall effect current sensing devices which, in one embodiment, is fabricated as part of a power semiconductor device.

Abstract: A novel illumination device is provided which is small, inexpensive, and conveniently plugs into a standard power outlet, thereby allowing easy installation and deinstallation by nontechnical consumers, and thereby allowing the security light to be easily moved to any wall outlet as security needs change. This illumination device includes a motion detector so that the illumination is provided only in the presence of one or more persons who would find the illumination beneficial. A photoelectric device is provided such that the security light is illuminated in response to motion only when there is an insufficient amount of ambient light available from other sources. In one embodiment, a vision restrictor is provided such that motion is detected only from a desired detection area. In one embodiment, a vision extender is utilized in order to optimize the field of view for the motion detector, making the device more useful in narrow hallways and other unique installations.