Abstract: A programmable read only memory includes a transistor having an N type source, an N type drain, and a polysilicon floating gate extending over the channel between the source and drain. The floating gate also extends over and is capacitively coupled to an N well. By applying an electric potential to the N well, the potential on the floating gate above the channel is altered.Within the N well is a P region, which mitigates the decrease in capacitive coupling between the N well and the floating gate caused by carrier depletion.

Abstract: A corrosion resistant electrical interconnect system has a flexible circuit with buried conductor patterns in an insulative film coating which is juxtaposed to a feed-through connector having inlet/outlet electrical contact pins therethrough. Sharp ends are present on the pins which pierce the insulative film and permit spot welding of the pin tips to portions of the conductor pattern. Other portions of the conductor pattern extend exteriorly of the flexible circuit and are electrically connected on to bond pads of an integrated circuit chip such as a sensor chip utilized in a mass flow meter.

Abstract: A linear motion rolling-contact bearing assembly includes a trough-shaped rail extending straight over a length and provided with outer guide grooves, a slider member provided with inner guide grooves each opposite to the corresponding one of the outer guide grooves and including an endless circulating path comprised of a load path section and non-load path section, a plurality of balls arranged in the endless circulating path which are brought into rolling contact with the corresponding pair of the inner and outer guide grooves at the load path section, and a retainer plate for retaining the balls in the endless circulating path while rolling along its load section. In accordance with the present invention, the slider member, received in the rail, includes a saddle-shaped table and a pair of upper and lower wall sections, which define therein at least the non-load path section of the endless circulating path and which are fixedly attached to the table by a fixing means, such as rivets.

Abstract: A controlled flow of X-ray attenuating gas such as helium is provided to an upper portion of a beam exposure chamber. A vent tube (21) extends from a lower portion of the chamber adjacent a mask to an exterior exit orifice (23) positioned at mask level to prevent ingress of air to the chamber and prevent mask membrane deflecton and change in the mask-to-silicon wafer substrate gap distance. The substrate (20) is positioned below the mask membrane and is surrounded by a mask-to-wafer zone into which is flowed a substrate fabrication process gas which is vented either by a gas flange (25) in spaced gapped relation to the mask holder and mask, or by a vent tube (46) extending from the zone to an orifice end (46a) approximate the level of the mask. There is then no pressure differential on the top and bottom surfaces of the mask membrane affecting the mask-to-wafer gap distance (8) during substrate fabrication operations.

Abstract: A current source for powering programmable arrays which provides means of eliminating the current supplied to portions of the array which are unimportant to the boolean arithmetic equation which the programmable array is programmed to model. The circuit includes fusible links (33-1 through 33-M) between the current source and portions of the circuit which may be unnecessary. Also included is means of opening (13-1 through 13-M) the fusible links (33-1 through 33-M) which connect the current source with the elements of the programmable array which may be unnecessary, thereby saving the power used to generate the current which would have been wasted in driving the unnecessary portions of the programmable array.

Abstract: A programmable read-only memory (40) is provided which is capable of storing a plurality of initialize words. The memory includes an initialize input lead (9) and appropriate addressing circuitry (7) so that when the appropriate initialize input signal is placed on the initialize input lead, one of several pre-programmed initialize words is placed in the output register (6) of the programmable read-only memory. The word that is placed in the output register is selected according to signals applied to selected address input leads (A.sub.0 through A.sub.3) of the programmable read-only memory. The number of address input signals utilized to determine which initialize word is placed in the output register of the programmable read-only memory is a selected subset of the available address input signals provided to the memory. The described embodiment provides sixteen initialize words using a minimum number of components.

Abstract: A circuit constructed in accordance with this invention is described which includes a programmable chip enable-output enable buffer (11-X). The chip enable-output enable buffer may be programmed to provide a chip enable function in response to a logical 1 or logical 0 chip enable input signal, an output enable function in response to a logical 1 or logical 0 output enable input signal, or an active powered chip regardless of the provided input signal. The chip enable-output enable buffer is programmed by "programming" selected transistors in the buffer. A P channel transistor (40, 60) is programmed by causing its source to be connected to its drain. An N channel transistor (50, 60) is programmed by causing its source and drain to be disconnected. In one embodiment, the programming is accomplished in the preferred embodiment by either a diffusion process or an ion implantation process.

Abstract: A special interconnect circuit which connects adjacent configurable logic elements (CLEs) in a configurable logic array (CLA) without using the general interconnect structure of the CLA. In one embodiment, an array of CLEs is arranged in rows and columns and a special vertical lead circuit is provided which connects an output lead of a given CLE in a given column to a selected input lead of the CLE above it and below in the same column. Special horizontal lead circuits are provided which connect a given output lead of a given CLE to a selected adjacent input lead of the CLE in the same row.

Abstract: A high speed M-stack fall-through FIFO memory system is disclosed which reduces fall-through delay and which permits at least a doubling of the maximum shift rates at input and output ports. Input port data may be entered in one of M physical memory locations and output port data may be read from one of M physical memory locations.

Abstract: A method for curing athlete's foot includes a step of carrying out an irradiation of a laser beam having the energy density of 2 Joules/cm.sup.2 for a time period of 10 milliseconds or less to the affected part of a patient's foot.

Abstract: A self-aligned split gate single transistor memory cell structure is formed by a process which self aligns the drain region to one edge of a floating gate. The portion of the channel underneath the floating gate is accurately defined by using one edge of the floating gate to align the drain region. The control gate formed over the floating gate controls the portion of the channel region between the floating gate and the source to provide split gate operation. The source region is formed sufficiently far from the floating gate so that the channel length between the source region and the closest edge of the floating gate is controlled by the control gate but does not have to be accurately defined.

Abstract: Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a reference fusible link to detect the presence or absence of a short circuit.

Abstract: A DC to square wave inverter (100) includes a saturable transformer (T102). The current through the saturable transformer (T102) is determined by the load current of the inverter (100). Current through the saturable transformer (T102) flows through two diodes (D100, D101) and through the base emitter junction of a power transistor (Q101). As the load current increases, the current through the diodes (D100, D101) and the power transistor (Q101) increases. This causes an increase in the voltage across the saturable transformer (T102), thus decreasing the amount of time it takes for the saturable transformer to go into saturation. A negative resistance element is coupled in series between the diodes (D100, D101) and the saturable transformer (T102). The voltage rise across the negative resistance element increases in response to increased current coming out of the saturable transformer (T102) and through the diodes (D100, D101).

Abstract: The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead.

Abstract: A unique method and structure is provided for testing high voltage equipment with great accuracy of voltage levels to be measured, repeatability of measured levels from one piece of test equipment to the next, no need for recalibration of test equipment, and sufficiently low current during testing that the test equipment can be powered by the same supply that powers the device under test. The device of this invention can be used to measure not only logical one and logical zero voltage levels of the device under test while under specific loads but can also be used to meausre transition time from one logic state to another.The circuit of this invention provides an output signal which can have three states reflecting a high logic level from the device under test, a low logic level from the device under test, and an intermediate level indicating that the device under test is in transition from one logic level to another or has failed the test.

Abstract: A carrier is provided to hold a central apertured disk while magnetic material is plated simultaneously on the annular surfaces on both sides of the disk. The carrier contains a first opening substantially the same diameter as the disk and a second opening formed about a center line offset from the center line of the first opening so as to form a recess around a portion of the edge of the first opening. The disk is inserted into the first opening and recess to block the flow of plasma and impurities from one side of the disk to the other during the disk surface coating. A two-part plug is provided for placement in and sealing the center aperture of the disk. One plug part contains a spring or magnetic means for holding the two parts together within the disk. The plug includes a knob for handling, carrying and mounting or removing the disk from the carrier.

Abstract: A unique double inversion buffer has a first means to invert and isolate the digital input signal, a second means to reinvert and further isolate the input signal, and an output means including an output transistor 94. The double inversion buffer is configured with active pull-down means on the output transistor 92. The high-to-low propagation delay time and the low-to-high propagation delay times through the double inversion buffer and reduced by use of the active pull-down means. Rapid turnoff of the output transistor is accomplished by coupling a transistor to its base to instantaneously turn it off. In a preferred embodiment, a clamping circuit 201 is used to hold the output voltage at a maximum predetermined level to further reduce the time it takes to reduce the output voltage to the logical "0" state.

Abstract: Voltage controlled oscillator (50) provides an exponential transfer function. The frequency of the output signal of the voltage controlled oscillator varies exponentially with the input voltages (V.sub.IN1, V.sub.IN2) to the oscillator. The exponential transfer characteristic is provided by means of a MOS field effect transistor (19) biased in its subthreshold range.