Abstract: A semiconductor memory device which is capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption despite the quick chip enable access. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level, and having a plurality of transistors whose gate lengths are set to first dimensions, and a second input buffer activated in response to both another input signal having a TTL level and the signal having the CMOS level, and having a plurality of transistors whose gate lengths are set to second dimensions greater than the first dimensions.
Abstract: An electronic device (21) switches its operation mode in accordance with the type of an installed battery pack (22). The battery pack (22) has a regulator (222), a specification-discriminating terminal (TJ), and a resistor (224), connected between the regulator (222) and the specification-discriminating terminal (TJ) and having a resistance corresponding to the specification of the incorporated battery (221). The electronic device (21) has a monitor resistor (214) connected between a terminal (TL) connected to the specification-discriminating terminal (TJ) of the battery pack (22) and ground, a discriminating circuit (212, 215, 216) for detecting a monitor voltage generated across this monitor resistor (214) to discriminate the specification of the battery (221), and a switch controller (212, 219) for switching the operation mode in accordance with the specification discriminated by the discriminating circuit (212, 215, 216).
Abstract: A method of manufacturing a one-transistor one-capacitor memory cell structure. In a first step, a buried insulating film layer is formed in a semiconductor substrate and a semiconductor layer is formed on the buried insulating film layer. In a second step, a capacitor trench is formed in the substrate by penetrating through the buried layer and a dielectric film layer is formed on an inner side wall surface of the trench. Then, a conductive material is filled into the trench to form a capacitor. Finally, an MIS transistor is formed in the semiconductor layer adjacent to the trench capacitor such that either the drain or the source makes contact with the conductive material.
Abstract: An electrical connector for electrically connecting to a card medium having electrical connecting terminals. The electrical connector includes a case having a horizontal surface including opposite first and second sides, and an inclined surface including opposite third and fourth sides, wherein the fourth side is connected to the first side and the inclined surface is inclined so as to descend from the fourth side toward the third side. Supporting structure is provided opposite to the inclined surface for supporting contacts provided at the side thereof opposite to the inclined surface. A fixing structure is provided for fixing the card medium when the card medium is inserted between the inclined surface and the contacts in a state where the electrical connecting terminals contact the corresponding contacts.
Abstract: A method of performing trench isolation in a CMOS transistor, that produces no latch-up and results in an effective isolating structure without using an epitaxial growth process. A field oxide layer is provided on a silicon substrate to isolate an active region. A first conductivity-type well is formed at a predetermined position of the active region. A gate oxide layer, a polysilicon layer and a silicide layer are deposited in sequence. A first gate electrode and a second gate electrode are formed by lithography and etching techniques wherein the first gate electrode is on the well, and the second gate electrode is on the active region outside the well. A silicon nitride layer is deposited and etched back to form spacers on the side walls of the electrodes whereby slits are left between the field oxide layer and the spacers and between adjacent spacers. Trenches are formed by etching the silicon substrate in the slits.
Abstract: A snowboard has a pair of bindings for a person's footwear. Each binding includes a laterally spaced apart independently moveable pair of binding straps and latches that can be engaged in latched positions over the vamp of the footwear for binding the footwear to the snowboard. On each binding, a release strap is connected between the two latches, so that by pulling on the release strap in a direction away from the snowboard's upper surface, forces are applied to actuation members of both latches so as to release both binding straps from their latched positions.
Abstract: An electrophotographic development apparatus capable of maintaining the surface roughness of a developer roller thereof for a long term or even for the life span of the apparatus. The developer roller includes an elastic layer, formed on a core metal shaft, and made of a rubber elastic material with additional insulating micro-powder of 30 to 200 parts having a particle diameter in a range of 1 to 50 micrometers, where the amount of the rubber elastic material constitutes 100 parts. During a printing operation, the insulating micro-powder drops from the elastic layer as the rubber elastic material is worn, so that the developer roller can maintain its surface roughness in proportion to the particle diameter of the dropped powder.
Abstract: A semiconductor integrated circuit includes an internal circuit, and ground and power supply lines for activating the internal circuit. An output MISFET is activated by peripheral circuit ground and power supply lines. For protection of the internal circuit from the effects of ground or power supply line noise, an impedance electrically separates the power supply lines for the internal and peripheral circuits and/or the ground lines for the peripheral and internal circuits. A surge protection circuit is provided between the gate of the output MISFET, and either or both of the ground and power supply lines for the peripheral circuitry.
Abstract: A power control circuit having a saturation preventing control loop including a variable gain amplifier, an RF power amplifier, a directional coupler, a detecting circuit, a comparator, a switch, and an adder. When the signal level of an output signal of the comparator is low, the switch is turned on. When the signal level of the output signal of the comparator is high, the switch is turned off. A system power control loop includes a system power control terminal, the adder, and the variable gain amplifier. Since the saturation preventing control loop is provided with the switch, the saturation preventing control loop operates only when the signal level of the amplified signal is larger than a reference value. The system power control loop can properly operate according to a system power control signal supplied from the system power control terminal.
Abstract: A highly stable sense amplifier circuit for a RAM and ROM includes a bias generating circuit capable of changing a bias voltage corresponding to voltage shifts of data lines, and an amplifying circuit having a transistor, the conducting state of which is controlled by the bias voltage for amplifying the voltage differences of the data lines. When the voltage of the data lines shifts due to manufacturing deviations, the bias voltage also shifts but operates so as to compensate shifts of the transistor in the amplifying circuit, so that the sense amplifier circuit can amplify the voltage differences of the data lines in a stable manner. The sense amplifier circuit can be formed with switches for cutting off through-currents, so that the sense amplifier circuit or even the memory on which the sense amplifier circuit is formed can operate with low power consumption.
Abstract: A tire pressure drop alarm device for judging a pneumatic pressure drop by calculating rotational angular velocities of tires provided for a four-wheel vehicle. When the vehicle is traveling on a road which varies in condition between left and right sides, a front/rear ratio of rotational angular velocities of the tires at the shoulder side of the road changes more markedly than that of rotational angular velocities of the tires at the center side, and a large time differential value appears. Therefore, it is possible to judge the traveling condition of the vehicle when the road condition varies between left and right sides. When it is judged that the traveling condition of the vehicle encounters a road condition which varies between left and right sides, the tire rotation of the four wheels is likely to become unbalanced, giving a false alarm even if the tire pressure does not drop. In this case, the judgment by the pneumatic pressure drop judging means is inhibited to prevent an issuance of a false alarm.
Abstract: A word line driver has a decoder for outputting decode signals having first and second logic levels, level shifters for receiving the respective decode signals, each level shifter outputting drive signal having first and third logic levels in response to the received decode signal, the third logic level being higher than the second logic level; a pumping circuit for outputting word line activation signals, at least one of the word line activation signals having the third logic level; and groups of output circuits, each group having the output circuits connected to one of the level shifters and a word line, respectively, each of the output circuits outputting the word line activation signal to the respective word line in response to the decode signal and the drive signal.
Abstract: An automatic teller machine managing system includes an automatic teller machine and a carrier for exchanging a medium, such as, paper money, with the automatic teller machine. The system further includes a mechanism for moving the carrier relative to the automatic teller machine, and a coupling unit which is movably arranged and couples the carrier and the automatic teller machine with each other. In the system, the medium is carried one by one, via the coupling unit, from the carrier to the automatic teller machine or from the automatic teller machine to the carrier.
Abstract: A method of fabricating memory cells with buried bit lines. In this method, a pad oxide layer is formed on a first conductivity-type silicon substrate. A photoresist layer is formed on the pad oxide layer while exposing predetermined areas of channels. A thick oxide layer is deposited by liquid phase deposition (LPD). The photoresist layer is removed. Second conductivity-type impurities are implanted to form source-drain electrodes using the thick oxide layer as a mask. The thick oxide layer and the pad oxide layer are removed to form bit lines and then word lines are formed crossing the bit lines, whereby the structure with buried bit lines and an array of memory cells is completed.
February 12, 1996
Date of Patent:
December 17, 1996
United Microelectronics Corporation
Cheng-Hui Chung, Yi-Chung Sheng, Belle Chia
Abstract: A code-division multiple-access receiver carries out the following steps whenever it recognizes a symbol boundary in the received baseband signal. First, using the despreading code of the relevant station, it estimates the value of the symbol. Next, using the spreading code of the station, it estimates an interference signal, and modifies the baseband signal by subtracting the interference signal. These steps can be iterated for each symbol. The iterations can be organized into stages, with estimated symbol values from one stage passed to the next stage for use in estimating new symbol values in that next stage. At the end, the remaining baseband signal can be used to adjust the final estimated symbol values.
Abstract: A dynamic RAM having a TAG address holding circuit in a TAG block in correspondence with one of a plurality of sub-arrays to hold the lower bits of an X (row) address. A block control circuit in the TAG block determines a "Hit" or "Miss" in accordance with the held address and a new X address in response to the sub-address and outputs a TAG determination signal. In response to the TAG judgment signal, a sub-array control circuit transfers a signal for access to the TAG block and a column sense amplifier. The column sense amplifier is utilized as a cache and data latched in the column sense amplifier are read out on a data bus when a "Hit" is determined.
Abstract: A coherent phase-shift keying (PSK) detector in a receiver generates an unmodulated carrier signal, without attempting to synchronize the unmodulated carrier signal in frequency or phase to the carrier employed at the PSK transmitter. The instantaneous phase of the received PSK signal is detected with reference to the unmodulated carrier signal to create an instantaneous phase signal. Phase rotation due to frequency offset between the two carrier signals is detected and removed from the instantaneous phase signal, then a remaining phase offset is detected and removed. Data are recovered from the resulting instantaneous phase signal.
Abstract: There is provided a resonant circuit incorporating at least a coil L1 therein and a switching circuit for oscillation is connected to the resonant circuit and voltage doubler rectifier circuits 31 and 32 including capacitors C11, C12, C21 and C22 and diodes D11, D12, D21 and D22 are also connected to the resonant circuit. When the switching circuit for oscillation is turned on and off, the resonant voltage V.sub.L1 is generated in the resonant circuit and rectified with a voltage doubler amplitude by the voltage doubler rectifier circuits 31 and 32. A switching circuit for output changing over is connected to zero voltage terminals of the diodes D11 and D21 in the voltage doubler rectifier circuits 31 and 32. When the switching circuit for output changing over is turned on and off, an output voltage is selectively generated at output terminals OUT1 and OUT2.
Abstract: A clock signal hull detector includes a signal level monitor for detecting an extraordinary condition in which the clock signal to be monitored is stuck at either a high level or a low level and a turning point number monitor for detecting an extraordinary condition in which the clock signal changes its level between the high and low levels with high frequency. The outputs of the signal level monitor and the turning point number monitor are fed to a fault judgment portion, which delivers an output according to the extraordinary conditions. The output of the fault judgment portion is then fed to a counting portion at which a fault judgment signal is fed to its output when its input signal is counted to a predetermined value or above.
Abstract: An optical device is disclosed which comprises a base including a lower cylindrical base member having a common central line and a first diameter and having top and bottom surfaces, a first electrode layer formed on the top surface of the lower base member, a dielectric layer formed on the first electrode, a second electrode layer formed on the dielectric layer, and an upper base member formed on the second electrode layer, the upper base member including a first cylindrical member having the common central line and the first diameter and having top and bottom surfaces, the bottom surface of the first cylindrical member faced on the second electrode layer and a second cylindrical member having the common central line and a second diameter smaller than the first diameter and having a top surface and a bottom surface faced on the top surface of the first cylindrical member; elongated leads supported by the base, the leads being elongated so as to protrude from the bottom surface of the lower base member; a ring