Patents Represented by Attorney, Agent or Law Firm Stuart H. Mayer
  • Patent number: 6658181
    Abstract: A method and apparatus provides a WDM optical signal having a plurality of channels with a pair-wise orthogonal polarization state. The method begins by receiving a plurality of unpolarized optical wavelengths defining a plurality of optical channels separated by a prescribed channel spacing. A polarization wavelength dependent shift is imparted to the optical wavelengths, which is substantially equal to a particular fraction of the prescribed channel spacing.
    Type: Grant
    Filed: January 2, 2002
    Date of Patent: December 2, 2003
    Assignee: Wavesplitter Technologies, Inc.
    Inventors: Yan Wang, Yuan P. Li
  • Patent number: 6656797
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer. A second doped layer is formed in the same manner as the first doped layer. The second doped layer is located vertically below the first doped layer.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: December 2, 2003
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6657256
    Abstract: A trench DMOS transistor having overvoltage protection includes a substrate of a first conductivity type and a body region of a second conductivity type formed over the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and overlies the body region. A conductive electrode is deposited in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. An undoped polysilicon layer overlies a portion of the insulating layer. A plurality of cathode regions of the first conductivity type are formed in the undoped polysilicon layer. At least one anode region is in contact with adjacent ones of the plurality of cathode regions.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: December 2, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So
  • Patent number: 6648906
    Abstract: A method and apparatus is provided for heating or cooling at least a selected portion of a patient's body. The method begins by inserting a catheter through the urethra and into the bladder of the patient. A heated or chilled fluid is conducted through a supply lumen of the catheter and into the bladder. The fluid is evacuated from the bladder through a return lumen of the catheter. Finally, a quantity of urine is monitored which flows out of the bladder and through the return lumen of the catheter. The rate of fluid flowing through the supply lumen of the catheter may be adjusted in a manner that is based at least in part on the monitored quantity of urine flowing out of the bladder.
    Type: Grant
    Filed: April 5, 2001
    Date of Patent: November 18, 2003
    Assignee: Innercool Therapies, Inc.
    Inventors: Juan C. Lasheras, Steven A. Yon, Michael Magers
  • Patent number: 6649477
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: November 18, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Patent number: 6631222
    Abstract: An optical switch includes at least one input port for receiving a WDM optical signal having a plurality of wavelength components, at least three output ports, and a plurality of wavelength selective elements each selecting one of the wavelength components from among the plurality of wavelength components. A plurality of optical elements are also provided, each of which are associated with one of the wavelength selective elements. Each of the optical elements direct the selected wavelength component that is selected by its associated selected element to a given one of the output ports independently of every other wavelength component. The given output port is variably selectable from among all the output ports.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: October 7, 2003
    Assignee: Photuris, Inc.
    Inventors: Jefferson L. Wagener, Thomas Andrew Strasser
  • Patent number: 6627949
    Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with an epitaxially layered material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: September 30, 2003
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6627951
    Abstract: A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: September 30, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So
  • Patent number: 6624494
    Abstract: A power semiconductor device and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer and a filler material is deposited in the trench to substantially fill the trench, thus completing the voltage sustaining region.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: September 23, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Patent number: 6619309
    Abstract: An excess flow valve includes a linear actuator that effectively isolates a defective CRT from others under preparation when the defective CRT causes the vacuum drawn on the exhaust cart to be compromised. During the manufacture of CRT's a manufacturing step requires that a vacuum be drawn on all CRT's while baking in an exhaust oven. This process is usually performed simultaneously on a plurality of CRT's connected to an exhaust cart by a manifold such that if a defect were to occur to one CRT that breaks breaking the vacuum, all the other CRT's under preparation would be compromised. This excess flow valve with the linear acutator and a method of operating it prevents excess damage to otherwise non-damaged CRTs.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: September 16, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Christopher Monks
  • Patent number: 6620691
    Abstract: A method for making trench DMOS is provided that improves the breakdown voltage of the oxide layer in a device having at least a first trench disposed in the active region of the device and a second trench disposed in the termination region of the device. In accordance with the method, mask techniques are used to thicken the oxide layer in the vicinity of the top corner of the second trench, thereby compensating for the thinning of this region (and the accompanying reduction in breakdown voltage) that occurs due to the two-dimensional oxidation during the manufacturing process.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: September 16, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui
  • Patent number: 6614953
    Abstract: An all-optical, optical cross-connect includes first and second pluralities of multiport optical devices. Each of the first plurality of multiport optical devices have at least one input port for receiving a WDM optical signal and a plurality of output ports for selectively receiving one of more wavelength components of the optical signal. Each of the second plurality of multiport optical devices have a plurality of input ports for selectively receiving one of more wavelength components of the optical signal and at least one output port for selectively receiving one of more wavelength components of the optical signal. At least one of the first or second plurality of multiport optical devices are all-optical switches that can route every wavelength component independently of every other wavelength component.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: September 2, 2003
    Assignee: Photuris, Inc.
    Inventors: Thomas Andrew Strasser, Per Bang Hansen, Jefferson L. Wagener
  • Patent number: 6611374
    Abstract: A method and apparatus is provided for controlling the optical output power from an optical amplifier arrangement. The arrangement includes a rare-earth doped fiber for imparting gain to an optical input signal propagating therethrough, a pump source for supplying pump power to the rare-earth doped fiber, and a tap for receiving a portion of the output power generated by the rare-earth doped fiber and converting it to a control signal. A controller is also provided for receiving the control signal and generating a bias current in response thereto for driving the pump source. The method begins by receiving an optical input signal that is being amplitude modulated at a prescribed frequency. The slew rate of the controller is adjusted so that the bias current drives the pump source to generate pump power that cannot vary at a rate greater than a slew-rate limit established by the controller. In this way resonance between the input signal and the frequency of the feedback control loop can be avoided.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: August 26, 2003
    Assignee: General Instrument Corporation
    Inventors: Eric James Converse, David Ciaffa, Charles John Donaldson
  • Patent number: 6593619
    Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: July 15, 2003
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6580141
    Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: June 17, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So
  • Patent number: 6576516
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A first layer of polysilicon having a second dopant of the second conductivity type is deposited in the trench. The second dopant is diffused to form a doped epitaxial region adjacent to the trench and in the epitaxial layer. A second layer of polysilicon having a first dopant of the first conductivity type is subsequently deposited in the trench. The first and second dopants respectively located in the second and first layers of polysilicon are interdiffused to achieve electrical compensation in the first and second layers of polysilicon.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: June 10, 2003
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6566201
    Abstract: A method for fabricating a high voltage power MOSFFT having a voltage sustaining region that includes doped columns formed by rapid diffusion. A high voltage semiconductor device having a substrate of a first or second conductivity type, an epitaxial layer of the first conductivity on the substrate, and a voltage sustaining region formed in the epitaxial layer, the voltage sustaining region including a column having a second conductivity type formed along at least outer sidewalls of a filled trench, the column including at least one first diffused region and a second diffused region, the first diffused region being connected by the second region and the second region having a junction depth measured from the trench sidewall that is less than the junction depth of the first region and a third region of a second conductivity type that extends from the surface of the epitaxial layer to intersect at least one of the first and second regions of second conductivity type.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: May 20, 2003
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6565222
    Abstract: A video projection device includes a cabinet having front and rear sections and a projection tube for projecting a video image. The video projection device also includes a screen located in the front section of the cabinet. The screen has a first surface onto which the video image is projected and a second surface for displaying the video image so that it is observable by a viewer. A mirror is arranged in the cabinet for reflecting light to the first surface of the screen. The mirror is a composite laminate mirror that includes a rigid substrate and a reflective sheet laminated to the rigid substrate. The rigid substrate may be a glass substrate and the reflective sheet may be a flexible plastic sheet. The reflective sheet may have a multilayer construction that includes a metallic film. The reflective sheet may alternatively include a second substrate and at least one thin film layer deposited on the substrate.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: May 20, 2003
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventors: Fusao Ishii, Joseph A. Marcanio
  • Patent number: 6554438
    Abstract: A video projection device includes a cabinet having front and rear sections and a projection tube for projecting a video image. The video projection device also includes a screen located in the front section of the cabinet. The screen has a first surface onto which the video image is projected and a second surface for displaying the video image so that it is observable by a viewer. A mirror is arranged in the cabinet for reflecting light to the first surface of the screen. The mirror is a composite laminate mirror that includes a rigid substrate and a reflective sheet laminated to the rigid substrate. The rigid substrate may be a glass substrate and the reflective sheet may be a flexible plastic sheet. The reflective sheet may have a multilayer construction that includes a metallic film. The reflective sheet may alternatively include a second substrate and at least one thin film layer deposited on the substrate.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: April 29, 2003
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventors: Fusao Ishii, Joseph A. Marcanio
  • Patent number: 6548860
    Abstract: A trench DMOS transistor structure is provided that includes at least three individual trench DMOS transistor cells formed on a substrate of a first conductivity type. The plurality of individual DMOS transistor cells is dividable into peripheral transistor cells and interior transistor cells. Each of the individual transistor cells includes a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. A conductive electrode is located in the trench, which overlies the insulating layer. Interior transistor cells, but not the peripheral transistor cells, each further include a source region of the first conductivity type in the body region adjacent to the trench.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: April 15, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui