Abstract: A method of forming a trench DMOS transistor is provides which reduces punch-through. The method begins by providing a substrate of a first conductivity type. A body region, which has a second conductivity type, is formed on the substrate. A masking layer is formed which defines at least one trench. Next, the trench and an insulating layer that lines the trench are formed. A conductive electrode is then formed in the trench, which overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. The step of forming the trench includes the steps of etching the trench and smoothing the sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.

Abstract: A trench DMOS transistor cell is provided, which is formed on a substrate of a first conductivity type. A body region, which has a second conductivity type, is located on the substrate. At least one trench extends through the body region and the substrate. An insulating layer lines the trench. The insulating layer includes first and second portions that contact one another at an interface. The first portion of the insulating layer has a layer thickness greater than the second portion. The interface is located at a depth above a lower boundary of the body region. A conductive electrode is formed in the trench so that it overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench.

Abstract: A method of forming a trench DMOS transistor is provides which reduces punch-through. The method begins by providing a substrate of a first conductivity type. A body region, which has a second conductivity type, is formed on the substrate. A masking layer is formed which defines at least one trench. Next, the trench and an insulating layer that lines the trench are formed. A conductive electrode is then formed in the trench, which overlies the insulating layer. A source region of the first conductivity type is formed in the body region adjacent to the trench. The step of forming the trench includes the steps of etching the trench and smoothing the sidewalls of the trench with a sacrificial oxide layer before removal of the masking layer that defines the trench.

Abstract: An apparatus is provided to compensate for dispersion in a transmission medium. The apparatus includes an input port for receiving a WDM optical signal having a plurality of signal wavelengths and a first Bragg transmission grating receiving the WDM optical signal from the input port. The first Bragg transmission grating has non-zero dispersion at at least one of the signal wavelengths. The first Bragg transmission grating also has a Bragg wavelength that is chosen so that all of the plurality of signal wavelengths lie outside of a reflection band of the first Bragg transmission grating. A second Bragg transmission grating, which is optically coupled to the first Bragg transmission grating, has a non-zero dispersion at at least one of the signal wavelengths. The second Bragg transmission grating also has a Bragg wavelength that is selected so that all of the plurality of signal wavelengths lie outside of a reflection band of the second Bragg transmission grating.

Abstract: Test structures for a high voltage MOSFET are provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. A plurality of trenches are located in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches. The test structures allow the simultaneous optimization of the breakdown voltage and on-resistance of the device.

Abstract: A semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is also formed within the first region, which also has sides and a bottom. A second region of semiconductor material is located within the first region and adjacent to and near the bottom of the gate trench. The second region extends to a location adjacent to and near the bottom of the drain access trench. The second region is of the first conductivity type and has a higher dopant concentration than the first region. A gate electrode is formed within the gate trench. A layer of gate dielectric material insulates the gate electrode from the first and second regions. A drain region of semiconductor material is located within the drain access trench. The drain region is of a first conductivity type and has a higher dopant concentration than the first region.

Abstract: A power semiconductor device and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer and a filler material is deposited in the trench to substantially fill the trench, thus completing the voltage sustaining region.

Abstract: A trench DMOS transistor cell includes a substrate of a first conductivity type and a body region located on the substrate, which has a second conductivity type. At least one trench extends through the body region and the substrate. An insulating layer lines the trench and a conductive electrode is placed in the trench overlying the insulating layer. A source region of the first conductivity type is located in the body region adjacent to the trench. The source region includes a first layer and a second layer disposed over the first layer. The first layer has a lower dopant concentration of the first conductivity type relative to the dopant concentration of the second layer.

Abstract: A semiconductor device includes a first region of semiconductor material, which is doped to a first concentration with a dopant of a first conductivity type. A gate trench formed within the first region has sides and a bottom. A drain access trench is also formed within the first region, which also has sides and a bottom. A second region of semiconductor material is located within the first region and adjacent to and near the bottom of the gate trench. The second region extends to a location adjacent to and near the bottom of the drain access trench. The second region is of the first conductivity type and has a higher dopant concentration than the first region. A gate electrode is formed within the gate trench. A layer of gate dielectric material insulates the gate electrode from the first and second regions. A drain region of semiconductor material is located within the drain access trench. The drain region is of a first conductivity type and has a higher dopant concentration than the first region.

Abstract: The total implementation complexity of packet schedulers which aim at approximating the Generalized Processor Sharing (GPS) policy is the combination of the complexity of their system-potential function and the complexity involved in sorting the timestamps in order to select the packet with minimum timestamp for transmission. Given that several scheduling algorithms which use a system-potential function of O(1) complexity have been introduced (among them, the Minimum-Delay Self-Clocked Fair Queuing (MD-SCFQ) algorithm achieves optimal delay and excellent fairness properties), the major contribution to the total complexity comes from the task of sorting the timestamps every time a packet is transmitted or received, which is common to all GPS-related schedulers.

Abstract: A method is provided for allocating bandwidth to a subscriber in a service provider domain that is part of a packet switched network such as the Internet, for example. In accordance with the method, a number of shares of bandwidth are assigned to the subscriber based on an agreement between the subscriber and a service provider. A subscriber identifier and the number of shares assigned thereto are distributed to the routers in the domain of the service provider. The routers will in turn allocate bandwidth to packets they receive based on the number of shares assigned to the subscriber transmitting or receiving the packet. The subscriber may include one or more different user terminals that aggregate traffic onto a single datastream. The shares assigned to the user may denote absolute amount of bandwidth, or alternatively, may denote a relative bandwidth allocation.

Abstract: A method and apparatus is provided for determining an effective thermal mass of a patient. The effective thermal mass is employed to determine a gain factor used in a feedback control system controlling patient temperature. The method begins by inducing hypothermia or hyperthermia in at least a selected portion of the patient with a device having a heat transfer surface. Next, power is transferred between the device and the patient. A change in temperature over time, which arises in the selected portion of the patient, is measured while performing the step of inducing hypothermia or hyperthermia. Finally, an effective thermal mass is calculated based on the measured power and the measured temperature change over time.

Abstract: A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.

Abstract: A method and apparatus is provided that yields improved performance by modulating the optical phase and polarization of an optical signal with a periodic waveform having harmonic content that is more complex than that associated with a simple sinusoidal waveform. A phase modulator receives an optical signal onto which data has been modulated at a predetermined frequency. The phase modulator modulates the phase of the optical signal in a continuous manner with the periodic waveform with complex harmonics where the fundamental phase modulation frequency is equal to the same predetermined frequency at which the data is modulated onto the optical signal.

Abstract: A temporary self-adherence of the individual components in a stack of semiconductor components is accomplished by the use of adhesive bodies either separate from the solder preforms used in the stack or included within the solder in the form of a tacky paste. The adhesive bodies may comprise relatively high-purity water, and adhesion of the adjoining parts is achieved by the surface tension of the water. During a single heating step, preferably performed in a protective, non-oxidizing atmosphere, the water is completely evaporated while the solder preforms are heated to form the desired solder joints.

Abstract: A communications system is provided which supports asynchronous transfer mode (ATM) communications. An ATM multiplexer is located at a customer's premises and connected to customer premises voice and data equipment. A central office ATM multiplexer is connected to various different networks in the existing network infrastructure. The central office ATM multiplexer is preferably connected to networks such as a low-speed packet-switched network, a public circuit-switched network, a private line network, and a high-speed packet-switched network. The ATM multiplexer located at the customer premises preferably supports dynamic bandwidth allocation. Additional features provided by the communications system include the ability to provide different voice encoding schemes for different users based on calling party or called party information.

Abstract: A facility is provided for enhancing an operations support system so that, based on data generated as a result of an event occurring in an associated telecommunications network, the operations support system can predict the likelihood of the event occurring again in the network.

Abstract: Increased network security is provided by monitoring in real time one or more characteristics or attributes of telephone calls that are placed through the network and notifying the network customer (i.e., the party responsible for paying for the telephone calls), in real time, when the attributes are indicative of abnormal or fraudulent network usage. The network customer, once notified of the abnormal usage, is in a position to take steps to minimize unauthorized network usage. For example, the network customer can selectively block network usage, deny access to the network on a call-by-call basis, or trace the call to catch the unauthorized user while the call is still in progress.

Abstract: A lightwave communication system includes an optical distribution system for routing optical signals and a plurality of optical transmitters coupled to the optical distribution system. At least one of the optical transmitters has an amplified light emitting diode for generating an optical spectrum. At least one optical receiver is optically coupled to the optical distribution system.

Abstract: A method for forming an optical grating within a waveguide integrated on a substrate includes the step of depositing on a substrate successive layers of material constituting a waveguide such that the waveguide has a periodically varying width along a portion of its longitudinal axis. The deposition may be accomplished by depositing by selective area epitaxy at least some of the successive layers through a mask having a periodically varying width along at least one edge. The successive layers deposited through the mask may constitute a plurality of quantum well layers separated from each other by barrier layers which collectively form a multiple quantum well stack.