Abstract: A micromachined capacitor structure having integral travel stops (19, 22, 22') within an active region of the capacitor is provided. The capacitor structure is formed on a substrate (11) and includes a moving capacitor plate (15) supported by one or more flexing arms (17) mechanically anchored to the substrate (11). The moving capacitor plate (15) has an active region (15) substantially parallel to the substrate (11) and separated from the substrate (11) by a first spacing. A corrugation (19) is formed in the moving capacitor plate (15) over the substrate (11) and separated from the substrate (11) by a second spacing, wherein the second spacing is smaller than the first spacing.

Abstract: A vertical conducting insulating gate bipolar transistor having an emitter region formed in a base region wherein the base region is not shorted to the emitter is provided. The emitter and base regions are formed in an upper portion of a lightly doped semiconductor drift region and an anode region is formed in a bottom portion of the drift region. During forward conduction, minority carriers are injected from the anode into the base region, biasing the base region sufficiently to inject minority carriers into the upper surface of the drift region. The injected minority carriers improve conductivity in the upper portion of the drift region.

Abstract: A semiconductor probe card having a plurality of micromachined probes tips for contacting an array of electrode pads formed on a semiconductor integrated circuit is provided. The plurality of probe tips are formed on the top surface of the substrate wherein the probe tips are arranged in an array matching of electrode pads on the integrated circuit to be tested. A portion of the semiconductor substrate underneath the probe tips is thin, so that the probe tips rests on a flexible diaphragm or beam.

Abstract: A non-oxide ceramic (16) for electronic packages and a method of producing electronic packages using a non-oxide ceramic is provided. In accordance with the present invention, the non-oxide ceramic (16) is coated with silicon dioxide (15) and a bonding glass (14) having diboron trioxide is used to attach other package components such as semiconductor chips (18), leadframes (13), and heatsinks (11) to the non-oxide ceramic (16).

Abstract: An enhanced mobility semiconductor comprising a host quantum well having at least two charge carrier barrier layers of a wide bandgap material, each of the two charge carrier barrier layers being separated by a conducting region containing charge carriers is provided. A number of phonon barriers having a predetermined thickness are formed in the conducting region wherein the predetermined thickness is chosen to allow charge carrier tunneling through the phonon barriers.

Abstract: A handler (11) which transports a number of packaged semiconductor devices (12) in a boat (23) to a test head (14) and tests the devices (12) is provided. The handler (11) has an input staging section (29), a testing section (31) which is adjacent to the test head (14), and an output staging section (36). A boat transport (27a, 27b) moves the boat (23) from the input staging section (29) to the testing section (31) and from the testing section (31) to the output staging section (36). The boat transport (27a, 27b) operates during the device testing to provide substantially parallel operation of the testing and handling steps. A boat lift (39) moves the boat (23) to the test head (14) to allow the packaged semiconductor devices (12) to remain in the boat (23) during testing.

Abstract: An enhanced conductivity structure comprising first and second coupled quantum well channel layers spaced from each other by a barrier layer of predetermined thickness is provided. The barrier layer and other supporting layers comprise a first material type, while the first and second quantum wells comprise a second material type having a narrower bandgap than the first material type. Each of the quantum wells is thin to confine current flow to the plane of the quantum wells. First and second spacer layers of the first material type are formed adjacent to each of the quantum wells, and planar doping layers are provided on each of the spacer layers. First and second buffer layers of the first material type are formed adjacent to each of the spacer layers.

Abstract: A heterojunction field effect transistor structure having a plurality of vertically stacked field effect devices. Two or more devices having electrically independent source and drain regions are formed such that a single gate electrode controls current flow in each of the devices. Each of the vertically stacked FETs have electrically isolated channel regions which may be controlled by a single gate electrode. Vertically stacked devices provide greater device packing density.

Abstract: An insulated gate bipolar device is formed on a multiple conductivity substrate. The multiple conductivity substrate comprises interspersed regions of N+ and P+ semiconductor material. In a preferred embodiment, the N+ and P+ regions are arranged in a checkerboard, mosaic pattern on a bottom side of the substrate. The P+ region serves to conductivity modulate an N epitaxial layer in which the IGBT structure is formed while the N+ regions improve low current conductivity, reduce minority carrier recombination time, and make an integral drain source diode accessible from the drain and source electrodes.

Abstract: A real time automatic visual semiconductor package inspection method is provided wherein a direction edge enhancement is performed on an image of the package. The direction edge enhanced image is dilated and correlated to a stored direction edge shape to identify all shapes of interest in a package under inspection. Also, anomalous shapes and uncorrelated direction edge shapes are identified and dilated. The dilated direction edge shape is analyzed using relatively simple mathematic techniques such as counting the number of shapes of a particular type, transforming shapes of interest to identify points of interest, and measuring relative position between the points of interest to determine acceptability of the semiconductor package. Also, size and location of anomalous shapes are calculated to determine acceptability of the package.

Abstract: An automatic integrated circuit inspection method is provided wherein an image of an integrated circuit is obtained and a direction edge enhancement is performed. An image of an integrated circuit under inspection is then obtained and the direction edge enhancement performed. The second edge enhanced image is then logically compared to the first edge enhanced image. Preferably, the first edge enhanced image is dilated while the second edge enhanced image is skeletonized to improve robustness of the system allowing for magnification and rotation errors in either the sample image or the image under inspection. Further, defects which are located are then classified by obtaining a plurality of images of the defect while changing light conditions. The plurality of defect images are combined to form a feature matrix which is then compared against an expert system database having a large number of feature matrices associated with defect classifications.

Abstract: An elastic material covering an outer surface of a cavity plate but not covering any clamping surfaces of the cavity plate or the inner surface of the cavity plate is used to eliminate use of a dam bar in a lead frame. In an embodiment in accordance with the present invention the elastic material provides a supplementary seal to the clamping surfaces of the cavity plate and a primary seal in spaces between leads of the encapsulated lead frame. In a method of using the present invention, the elastic material is placed between the mold base and the cavity plate. A semiconductor lead frame to be encapsulated is placed in cavities provided by the cavity plate. The mold is closed so that clamping surfaces of the cavity plate clamp directly onto the leads. The elastic material deforms under pressure to compensate for any dimensional variations of the mold plates or lead frame and completely seals the space between leads.

Abstract: A means and method for forming improved merged complementary bipolar, complementary MOS (CBICMOS) structures is described. The N-channel and N-base devices are gouped in a first isolated semiconductor region and the P-channel and P-base devices are grouped in a second isolated semiconductor region. The two regions are separated by lateral isolation. By sharing internal device regions and arranging the internal device regions in the proper sequence a particularly compact structure is obtained which may be wired to implement a variety of CBICMOS circuits using a single wiring layer. Both CMOS and vertical NPN and PNP bipolar devices are produced in a common substrate by a common process.

Abstract: A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is coupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

Abstract: A visual lead-finger inspection method is provided comprising obtaining an image of a semiconductor package and enhancing an image of lead-fingers which are a part of the package. In a first embodiment the image enhancement comprises morphological opening, and in an alternate embodiment comprises direction edge enhancement. A logical AND operation is performed with the enhanced lead-finger image and a frame image which is placed through the lead-finger image, resulting in a data set of only a few hundred bytes which describes position, alignment and lead count of all of the lead-fingers on the package. The data set is compared to a stored data set to determine acceptability of the semiconductor package.

Abstract: A micro-mechanical sensor having a field effect transistor formed in a proof mass portion of a substrate is provided. The proof mass portion is attached to a support portion of the substrate by a means for flexing such as a diaphragm or cantilever beam. A gate electrode is formed over a channel region of the field effect transistor and separated from the channel region by a gap whereby force applied to the sensor causes the proof mass portion to move towards the gate electrode due to flexing of the flexing means. As the channel region moves closer to the gate electrode, current flows through the field effect transistor generating an output signal.

Abstract: A buried interconnected transistor and capacitor are formed in a trench etched in a semiconductor wafer having a lightly doped surface layer. The trench extends through the surface layer into the substrate. A dielectric liner is provided in the trench and the trench partially refilled with polysilicon up to the surface layer. The dielectric liner is removed thereby exposing sidewalls of the surface layer in the trench. Further silicon is deposited which forms additional poly material on the poly plug, single crystal material on the exposed epi-sidewalls, and further poly above the single crystal material. A dielectric is formed over the deposited material and a gate electrode deposited over the single crystal portion on the sidewall. The poly plug serves as one plate of a buried trench capacitor and the single crystal material accommodates the channel of the series MOSFET connected to the poly plug capacitor plate.

Abstract: An improved semiconductor AC switch is described having internal bias generation for the power MOSFET switches and isolated control input. Dual power MOSFETS with substrate diodes are connected in series between source and load. DC gate bias for the MOSFETS is derived from an internal power supply containing energy storage which charges from the line, typically every half cycle. The gates of the power MOSFETS are tied to the internal bias generator through a voltage divider network containing a variable resistance controlled by an optical input signal. The internal energy storage may be a capacitor or solid state battery, preferably a monolithic thick or thin film battery. No transformers or external control bias generators are required and the resulting switch is particularly simple and compact.

Abstract: MOSFET devices or circuits incorporating an improved substrate temperature sensing element are obtained by forming a PN junction directly on a thin (gate) dielectric region. The temperature sense junction is desirably formed in a poly layer. By mounting it directly on thin (gate) dielectric its thermal response to temperature changes in the substrate is improved while still being electrically isolated from the substrate. It is desirable to provide over-voltage protection elements coupled to the junction to avoid rupture of the underlying thin dielectric. Because the sense diode and all the over-voltage protection devices may be made of poly with junctions perpendicular to the substrate, the structure is particularly compact and simple to fabricate.

Abstract: An index of refraction sensor having a photo detector array with variable sized elements is provided. The photo diode array comprises a plurality of diodes with varying area. The diodes farthest from a light emitting diode having a larger area than those closer to the light emitting diode. Preferably the diode area is designed so that each of the diodes produces approximately the same current output when exposed to light from the LED. Each diode in the photo diode array is sequentially powered and the photo diode outputs are summed together. A power input from a first diode in the array is coupled to a start input of a time measurement circuit. The summed output of the photo diode array is coupled to a stop input of the time measurement circuit. Elapsed time measured by the time measurement circuit is thus a function of reflected light edge location, and therefore a function of index of refraction of the fuel mixture.