Abstract: A heterojunction field effect transistor (HFET) having a source, drain, and channel, wherein the channel comprises a quantum well and at least one mono-atomic well or barrier layer is provided. The mono-atomic well or barrier layer has a different bandgap than the channel region and serves to modify electron wave function and conduction band energy in the channel region. Preferably, an indium arsenide well monolayer is formed in an InGaAs channel region and functions to move a first quantized energy level E.sub.0 closer to the bottom of the channel region quantum well thereby increasing electron concentration by increasing effective band offset potential. Another embodiment uses an aluminum arsenide monolayer as a barrier monolayer in the InGaAs channel. By varying location of the monolayers, confinement of electrons in the channel can be improved.

Abstract: A high voltage semiconductor structure having multiple guard rings is provided, wherein an enhancement region, which is of an opposite conductivity type from the guard rings, is formed between the guard rings to increase punch-through voltage between the guard rings. A floating field plate ring is formed over each guard ring, capacitively coupled to each guard ring. Each floating field plate has a flap extending beyond the guard ring in the direction of a main PN junction. The floating field plates serve to reduce parasitic coupling between adjacent guard rings.

Abstract: An ECL logic circuit having differential inputs and differential outputs and programmable propagation delay time is provided. The differential inputs are coupled to a first differential amplifier as is done on a conventional differential ECL circuit. A second feedback differential amplifier is coupled to the collectors of the first differential amplifier. Current in the first differential amplifier is normally constant, whereas current in the feedback differential amplifier can be programmably adjusted. By adjusting the current in the feedback differential amplifier the feedback differential amplifier loads the logic circuit forcing a voltage swing which is up to double that normally provided by the first differential amplifier, therefore increasing the time required for either output to change from a logic LOW to a logic HIGH. This delay results in a variable propagation delay which is controlled by adjusting current flow in the feedback differential amplifier.

Abstract: A superlattice structure comprising a host quantum well with a plurality of mini quantum wells formed therein is provided. The host quantum well has a confined energy state E.sub.2 which lies very near a lower band energy V.sub.1 of the host well, while each of the mini quantum wells has a single confined energy level E.sub.1 which lies below V.sub.1. Charge carriers are provided to the quantum well by doping material in the barrier layers to provide modulation doping of the quantum well. The mini quantum wells contain at least one monolayer of another material within their boundaries. The monolayer material is preferably electrically inactive and is a source of phonons which are generated for the purpose of charge carrier-phonon coupling in order to cause charge carrier pairing. In a preferred embodiment a transfer quantum well is formed between the barrier region of the host quantum well and the outermost mini quantum wells. The transfer quantum well has an energy state which couples to the E.sub.

Abstract: A GaAs complementary HFET structure having an anisotype layer formed underneath the P-channel device gate is provided. The anisotype layer is heavily doped N-type and is formed in contact with a semi-insulating AlGaAs barrier of the P-channel FET. A pre-ohmic layer is formed over the anisotype layer and a gate electrode is formed over the pre-ohmic layer. In a first embodiment, the pre-ohmic layer comprises undoped gallium arsenide amd the gate electrode forms a Schottky diode with the pre-ohmic layer. The anisotype layer forms a semiconductor junction with the semi-insulating AlGaAs barrier wherein the semiconductor junction replaces or augments a conventional Schottky junction. In a second embodiment, the pre-ohmic layer comprises heavily doped InGaAs and the gate electrode forms an ohmic contact to the doped InGaAs. The semiconductor junction at the P-channel device gate results in higher built in potential barrier and improved P-channel gate turn on voltage.

Abstract: A heterojunction field effect transistor (HFET) having a source, drain, and channel, wherein the channel is a top layer of a superlattice buffer, eliminating the need for a thick buffer layer. The superlattice buffer comprises alternating barrier and quantum well layers which are thin enough to provide wide separation in energy bands within the quantum wells. In a preferred embodiment the channel comprises a quantum well and one to five monolayers having a different bandgap than the channel region and serves to modify electron wave function and conduction band energy in the channel region. Preferably, a ten period AlAs/GaAs superlattice is formed underneath the channel.

Abstract: A configurable display comprising a distributed Bragg reflector having a plurality of flexible, compressible polymer layers is provided. The polymer layers are transparent and comprise alternating layers of differential index of refraction material so that a reflective surface is formed at each interface between the alternating layers. The polymer layers are sandwiched between a first electrode which is transparent and a second electrode. Thickness of each of the layers is designed such that light reflecting from the reflective surfaces interferes constructively at predetermined wavelengths. The thickness of each of the layers is altered by application of a static potential between the first and second electrodes which deforms the polymer layers thereby shifting the wavelength at which constructive interference occurs. In this manner wavelength and amplitude of reflective light can be modulated by a voltage applied between the first and second electrodes.

Abstract: A high voltage semiconductor structure having multiple guard rings, wherein guard rings farthest from a main junction are spaced further from each other than are guard rings closer to the main junction is provided. An enhancement region, which is of an opposite conductivity type from the guard rings, is formed between the guard rings to increase punch-through voltage between the guard rings, thereby increasing the breakdown voltage of the device. The enhancement region and close guard ring spacing result in a fine gradation of electric field and high punch-through breakdown voltage between guard rings.

Abstract: A monolithic diffraction spectrometer having a diffraction grating formed over a light sensing array is provided. The diffraction grating serves to diffract wavelengths of interest to an underlying photosensitive device while diffracting other wavelengths away from the photosensing element. By forming a diffraction grating with a variable pitch, or multiple diffraction gratings having various pitches, any number of specific light wavelengths can be detected with a high degree of precision. When a diffraction grating having a pitch which is in the order of the incident wavelength of light is used, improved sensitivity is achieved.

Abstract: An antimetastable state circuit which detects when a data edge is so close to a clock edge that it would result in a metastable state in a time measurement circuit is provided. When a potential metastable state is detected, the antimetastable circuit delays the data edge with respect to the clock edge by a known amount so as to avoid the metastable state. The delayed edge is used to start the time measurement circuit, and the next clock edge is used to stop the time measurement circuit. When the known delay has been added, it is subtracted from the measured time, to produce an accurate measurement of the elapsed time between the rise of the data edge and the rise of the clock edge.

Abstract: An enhanced conductivity superlattice made from semiconductor materials provides enhanced conductivity. It is believed that conductivity can be enhanced sufficiently to produce superconductivity well above typical superconductivity temperatures of the semiconductor materials. The enhanced conductivity quantum well is a superlattice structure having a monolayer phonon generator sandwiched between layers of a host material. Barrier layers surround the host material to confine the host material electrons. In another embodiment, the monolayer may be located within the barrier layers. The monolayer generates phonons having an optical energy which is lower than the optical energy of the host material. The generated phonons couple with low energy electrons or holes to propagate without dissipation of electron energy.

Abstract: A method of testing unpackaged integrated circuits using a tester which is capable of testing a plurality of memories in parallel is provided. A membrane test head having a plurality of probe bumps thereon is provided wherein the probe bumps are coupled to the tester by microstrip transmission lines formed on the membrane test head. The semiconductor memory has a plurality of contact pads thereon which are coupled to the probes. In this manner, a plurality of semiconductor memories can be tested in wafer form. Alternatively, individual semiconductor memory chips can be mounted on a receiver plate and tested individually or in parallel by moving the receiver plate so that the contact pads couple to the probes.

Abstract: An enhanced conductivity superlattice structure is provided in which a phonon generator embedded in a quantum well promotes formation of paired electrons. The superlattice structure provides electrons confined in a narrow energy gap material which is sandwiched between two barrier layers made of larger bandgap material. The electrons are provided to the quantum well by doping material in the barrier layers to provide modulation doping of the qnantum well. The quantum well contains at least one monolayer of another material within its boundaries which is a source of phonons which are generated for the purpose of electron-phonon coupling in order to cause electron pairing. In a preferred embodiment a plurality of phonon generator monolayers will be provided in the center of a quantum well, wherein the phonon generator monolayers are separated from each other by a few monolayers of quantum well material to provide increased number of phonons and therefore increased number of electron-phonon interactions.

Abstract: Apparatus and method of testing integrated circuits after the leads have been trimmed and partially formed, but before the package has been removed from the leadframe. One stage of a progressive trim and form process is adapted to test the integrated circuits by providing a membrane test head positioned underneath the IC package, wherein the membrane test head is coupled to an external tester. After the leads are electrically separated from each other end from the leadframe, the leads are aligned to the membrane test head and an inflatable bladder, which is positioned underneath the membrane test head, is inflated to couple the membrane test head to the leads. In this manner, one or more integrated circuits can be tested while still attached to the leadframe.

Abstract: A thermally protected power transistor comprising a first chip which includes a power transistor and a second chip which includes protection circuitry. The second chip has a plurality of metallic bumps formed thereon which are coupled to various portions of the protection circuitry, wherein at least one metallic bump serves as a thermal couple. The protection circuitry chip is mounted upside down on the power transistor chip and coupled to the power transistor chip by the metallic bumps. The metallic bumps serve to provide electrical power for the protection circuitry, to couple control signals between the protection circuitry and the power transistor, and to couple thermal information from the power transistor to the protection circuitry.

Abstract: An integrated circuit package having a low reflection input pin comprising a high frequency signal conductor internal to the semiconductor package is provided by coupling a first input pin to a second input pin with a conductive path, the conductive path having a constant characteristic impedance which matches the characteristic impedance of an external signal line which is coupled to the first input pin. A portion of the conductive path forms a bonding pad using for wire bonding, or other bonding technique, between the conductive path and a bonding pad of the integrated circuit. In this manner the impedance mismatch between an external signal conductor and the integrated circuit bonding pad is eliminated, and the total impedance mismatch between the semiconductor package and the external signal line is greatly reduced, resulting in higher frequency operation of the integrated circuit.

Abstract: A power transistor having a control electrode which is coupled to a polysilicon JFET transistor is provided. In particular, a power MOSFET device having a polysilicon gate is formed and a JFET transistor is formed in the same polysilicon layer which forms the gate of the power MOSFET. A drain of the JFET forms an input terminal for the power MOSFET and a source of the JFET is coupled to the gate of the power MOSFET. A gate of the JFET is copupled to a gate-drain diode clamp so that when the gate-drain diode clamp is activated a portion of the current which is used to turn on the power MOSFET is channeled to the gate of the JFET and increases the drain-to-source series resistance of the JFET. The resistance of the JFET is low during normal operation and increases only when the gate-drain clamp is activated thus provides a high resistance during avalanche stress protection and a low resistance during normal operation.

Abstract: An integrated circuit having both logic transistors and at least one power switching transistor formed on the same substrate is described, wherein both sets of transistors are powered by current received from the substrate, the power transistor being powered by current flowing directly from the substrate, and the logic transistors being powered by current flowing through a metal layer making electrical contact to the substrate.

Abstract: A light emitting diode is provided comprising a substrate which is transparent to the emitted light upon which a plurality of semiconductor layers, including a quantum well active layer, are formed. The materials are chosen not only for their optical characteristics but also so that many of the layers act as etch stops for layers which are formed on top of them. In addition to operational semiconductor layes which form the light emitting diode, two sacrificial semiconductor layers are formed on the substrate which serve as masks during processing and are removed prior to device metallization. An initial pattern is formed in the uppermost semiconductor layer and is transferred down through lower layers using the etch stop layers and selective etches so that further photolithography steps are unnecessary. Electrodes are formed on one side of the device by conventional metal deposition techniques and are self aligned to the LED junction.

Abstract: An interface apparatus for coupling a multi-channel tester to a high pin count logic circuit for use in testing the logic circuit is provided wherein a plurality of terminal electronics units are coupled to each test channel of the multi-channel tester. Some of the terminal electronics units are coupled to each other in parallel by at least one stimulus shift register, which serves to divide a serial stimulus vector among the terminal electronics units, and one response shift register, which serve to assembly the response data from several terminal electronics units into a serial response vector. The serial stimulus vector is generated, and the serial response vector is analyzed by the multi-channel tester. The apparatus is capable of operating in one of a plurality of modes used for functional testing, parametric testing, and high speed scan path testing of the logic circuit.