Patents Represented by Attorney Suiter-West
  • Patent number: 7293210
    Abstract: The present invention is directed to a system and method for improving transition delay fault coverage through use of augmented flip-flops (TL flops) for a broadside test approach. The TL flops use the same clock for scan and functional operation. Thus, the TL flops do not require a fast signal switching between launch and test response capture. Each of the TL flops includes additional multiplexer in front of a standard scan flop and a transition enable (TEN) signal. Moreover, only a heuristically selected subset of scan flip-flops is replaced with the TL flops and only one additional MUX per selected scan flip-flop may contribute an area overhead. Consequently, the overall chip area overhead may be minimal. The present invention may be suitable for being implemented with currently available third party ATPG.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: November 6, 2007
    Assignee: LSI Corporation
    Inventors: Arun Gunda, Narendra Devta-Prasanna
  • Patent number: 7260164
    Abstract: An efficient filter circuit and method for filtering a loss of receiver signal prevents false signals caused by glitches. The short glitches that happen at the positive edge of the clock signal may be prevented from affecting the whole clock cycle. The false signal removal circuitry is effective against both false active high and false active low signals. A selectable majority determination block also measures the number of glitches or average signal strength to determine that a valid signal is present. A mininum pulse width of a glitch is settable.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: August 21, 2007
    Assignee: LSI Corporation
    Inventors: Vijay Janapaty, Rishi Chugh, Rajinder Cheema
  • Patent number: 7134095
    Abstract: A user interface, system, method and software for displaying a simulated three-dimensional display of menu options to a user, thereby maximizing use of a display's real estate by presenting all available options at once while at the same time presenting certain options in a more pronounced manner. The system monitors for running applications, polls the running applications for any available options, and displays the options in the simulated three-dimensional format. With this type of dynamic menu, standard means for bringing focus to a selectable target create complexities, and are thus avoided by designing the system's cursor to duplicate the appearance of the selected target's shape, preferably in a smaller size.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: November 7, 2006
    Assignee: Gateway, Inc.
    Inventors: Kim C. Smith, Theodore David Wugofski, Michael Mostyn, Thomas A. Kayl
  • Patent number: 7134006
    Abstract: A method and system divides a media space, such as found in a hard drive or other mass storage device, into a portion directly accessible by all software and a portion inaccessible by all software except host Basic Input Output System (BIOS) code. A special procedure to access media space may include a special instruction or instruction set with or without a password to allow hard drive support for READ ONLY partitions, READ ONLY CD-ROM emulation, and other READ ONLY hard drive access requirements. The special procedure may user an expanded ATA command set, an expanded BIOS command set with System Management Mode, or code to temporarily unprotect at least a portion of the portion normally inaccessible by the software other than host BIOS code.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: November 7, 2006
    Assignee: Gateway Inc.
    Inventor: Edward P. Flanigan
  • Patent number: 7131050
    Abstract: The present invention is an apparatus and method for protecting against drive anomaly errors while optimizing random read performance. Data block persistency is explicitly verified when a data block is written. Data block integrity and location checks are performed by reading data from a single drive. Through such a process, reading of metadata from a second drive is not required, thus decreasing the drive I/O workload. In an example of the invention, a combination of a CRC and a location tag interleaved as metadata along with user data on a single drive may be employed to perform a read operation in accordance with the present invention.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: October 31, 2006
    Assignee: LSI Logic Corporation
    Inventor: Keith W. Holt
  • Patent number: 7127692
    Abstract: The present invention is directed to a timing abstraction and partitioning strategy for integrated circuit design. A method for designing an integrated circuit may include monitoring user interaction with logical blocks during a function design process of an integrated circuit. Indications of timing properties are derived during the functional design process.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: October 24, 2006
    Assignee: LSI Logic Corporation
    Inventor: Christopher L. Hamlin
  • Patent number: 7124901
    Abstract: A cooking device for cooking sweet corn allows the ears of corn being cooked to be suspended within a microwave oven cavity so that the corn may be cooked in a greatly reduced time compared to conventional cooking methods, while providing even cooking results. The cooking device comprises a base supporting one or more vertical supports capable of suspending ears of corn within a microwave oven cavity. Holders, inserted into the ends of ears of corn to be cooked, are received by the vertical support(s) for suspending the ear of corn.
    Type: Grant
    Filed: May 14, 2004
    Date of Patent: October 24, 2006
    Inventor: Chandra Stoupa
  • Patent number: 7123855
    Abstract: The present invention is an improved sealing strip for sealing the toner chamber slot of a toner cartridge, and its manufacturing method. A sealing strip for toner cartridges includes a sealing film and a double-faced sealing film adhered thereto. The sealing film includes, along a first direction, a sealing portion for sealing a toner chamber slot of a toner cartridge and a pull part extending along one end of the sealing portion. The pull part is used for tearing away the sealing portion. The sealing portion includes two openings adjacent the pull part. The two openings range from 0.5 to 3.5 millimeters in length. The sealing film includes, along a second direction substantially perpendicular to the first direction, a prime layer and a guide layer. The guide layer includes two guide lines substantially parallel to each other and extending along the first direction. The two guide lines intersect the two openings. The double-faced sealing film is adhered to the sealing portion.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: October 17, 2006
    Inventors: Yongjian Yuan, Lei Shi, Zhiyun Huang
  • Patent number: 7117323
    Abstract: The present invention is directed to a method and system for managing the coherency of mirrored storage volumes, including a method and system for restoring coherency in the event of communication disruption between the primary volume and the secondary volume mirroring the data on the primary volume. The system includes a primary and a secondary storage controllers for managing the primary and secondary storage volumes. The storage controllers are capable of performing cyclic redundancy checking scans of their respective storage volumes and comparing the results to determine data from the primary storage volume needed to update the secondary storage volume so that it mirrors the primary storage volume.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: October 3, 2006
    Assignee: LSI Logic Corporation
    Inventor: William P. Delaney
  • Patent number: 7117283
    Abstract: An extended protocol provides a serial bus with the capability of effective communications for a multimaster bus. A bus device may enter a master mode and transmit information identifying a designated recipient device on the bus. Either the master mode device or the designated recipient device may send information that identifies the master mode bus device. The master mode device may read from the designated recipient device or may write to the designated recipient device. The designated recipient device may provide an acknowledgement, data, a command, or status information may be sent back. The status information may include version information regarding the hardware, software, and/or firmware of the designated recipient device.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: October 3, 2006
    Assignee: LSI Logic Corporation
    Inventor: Matthew Trembley
  • Patent number: 7114133
    Abstract: The present invention is directed to a method and system for optimally mapping a general set of resources to a specific integrated circuit design. In an exemplary aspect of the present invention, a method for optimally mapping a general set of resources to a specific integrated circuit design may include the following steps. Sets of transistors are first abstracted into abstracted resources. The abstracted resources may include a transformative resource, a coordinating resource, and a state management resource, and the like. Then, a sea-of-platforms is utilized for unifying a flexible and malleable collection of the abstracted resources in such a way as to optimize the abstracted resources for a specific integrated circuit design. Broken symmetry may be used to optimize the abstracted resources for the specific integrated circuit design. The broken symmetry may be in at least one of a physical 3-dimensional space, a temporal space and a code space.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: September 26, 2006
    Assignee: LSI Logic Corporation
    Inventor: Christopher L. Hamlin
  • Patent number: 7114135
    Abstract: In an integrated circuit, test signals are routed from test points through a hierarchy of distributed multiplexers to output pads. The multiplexers are distributed locally to various regions that are arranged in a hierarchy of regional levels. Thus, each test signal is routed to the locally distributed multiplexer, and only a portion of the test signals reach the top-level multiplexer.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: September 26, 2006
    Assignee: LSI Logic Corporation
    Inventor: Coralyn S. Gauvin
  • Patent number: 7111242
    Abstract: A system and a method generate a device user interface executable by an information handling system. A device database includes a list of devices for which user interface components are available to implement functions for controlling the devices, and a resource database includes the user interface components. The device to be controlled by the user interface is identified and compared to a database of devices for which user interface resource components are available. A user interface generator determines whether the device is included in the device database and retrieves the user interface components from the resource database. A layout manager assembles the user interface components into a user interface. If the device is not listed, generic device user interface components are retrieved, otherwise device specific user interface components are retrieved, and assembled into a layout matrix. The user interface is created from the layout matrix.
    Type: Grant
    Filed: January 27, 1999
    Date of Patent: September 19, 2006
    Assignee: Gateway Inc.
    Inventor: Brandon A. Grooters
  • Patent number: 7106073
    Abstract: The present invention is directed to a system for area efficient charge-based capacitance measurement requiring a minimum silicon area for probe pads. A structure block for the system includes several test structures coupled to a target test capacitance structure, a reference structure, and a logic block. Each test structure is coupled to a corresponding test capacitance structure. The logic block coupled to the several test structures selects a desirable test structure from the several test structures. The system may include several structure blocks and an additional logic block to select a desirable structure block. Each structure block includes a single output pin for busing each test output from the several test structures. In this manner, the silicon area may be minimized through reduction of the number of total pins and probe pads required.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: September 12, 2006
    Assignee: LSI Logic Corporation
    Inventors: Randall Bach, Jeffrey Sather
  • Patent number: 7107483
    Abstract: An apparatus and method for enhancing data availability by leveraging primary/backup data storage volumes. A Remote Volume Mirroring (RVM) system may be leveraged according to the present invention to provide volume failover by enhancing the functionality of the arrays, in a manner transparent to the host operating system.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: September 12, 2006
    Assignee: LSI Logic Corporation
    Inventors: Kurt Duncan, Robert Stankey
  • Patent number: 7095609
    Abstract: A robust intuitive latching mechanism for securing an access panel to a chassis of an electronic device comprises a hook engagement member for engaging a hook coupled to the chassis to secure the access panel to the chassis. A spring member couples the hook engagement member to the access panel. The spring member is capable of flexing between a first position wherein the hook engagement member is engaged with the hook and a second position wherein the hook engagement member is disengaged from the hook. A handle assembly is mounted to at least one of the hook engagement member and the spring member for flexing the spring member. The handle assembly is actuated for flexing the spring member from the first position to the second position for disengaging the hook engagement member from the hook to allow the access panel to be removed from the chassis.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: August 22, 2006
    Assignee: Gateway Inc.
    Inventors: Vernon D. Erickson, David R. Davis, Derek T. Nguyen, Cesar Daniel Castillo, Armando Rocha, Richard A. Gibson
  • Patent number: D527972
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: September 12, 2006
    Assignee: Black & Decker, Inc.
    Inventors: Jeremy D. Leasure, Mark A. Etter
  • Patent number: PP17095
    Abstract: St. Augustinegrass ‘TR 6-10’ is a perennial St. Augustinegrass cultivar with dwarf turfgrass characteristics. ‘TR 6-10’ is a bright, dark green color and yet exhibits a dwarf, low growing habit. It is more wear tolerant than other St. Augustinegrasses and it is the most shade tolerant cultivar of a species that is highly regarded for this characteristic.
    Type: Grant
    Filed: August 19, 2004
    Date of Patent: September 12, 2006
    Inventor: Terrance P. Riordan
  • Patent number: D529025
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: September 26, 2006
    Assignee: Wenling Shuangyang Decoration Co., Ltd.
    Inventor: Lincong Yang
  • Patent number: D529026
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: September 26, 2006
    Assignee: Wenling Shuangyang Decoration Co., Ltd.
    Inventor: Lincong Yang