Abstract: A dual purpose PCI-X DDR configurable terminator/driver providing programmable termination of the interface in a PCI-X system a plurality of N-channel devices divided into at least two groups and a plurality of P-channel devices also divided into at least two groups. A driver control individually controls selected ones of the groups of N-channel and P-channel devices on or off for providing internal termination to the transmission line. The configurable PCI-X DDR driver/terminator is configurable in three termination modes: pull-up mode, pull-down mode, and symmetric mode.

Abstract: A host computer environment includes a driver stack having a disk driver and a host bus adapter (HBA) driver. The driver stack further includes a multipath driver functionally embedded between the disk driver and HBA driver. At this hierarchical layer of the driver stack, the multipath driver functions at the command transport protocol level. The disk driver effectively views the multipath driver as a HBA driver type, while the HBA driver effectively views the multipath driver as a disk driver type. The multipath driver is configured to instantiate proxy virtual paths to the disk array that are visible to the host operating system but otherwise conceal the underlying physical paths. The multipath driver retains knowledge of the mapping between the physical and virtual paths. The disk array is configured to report itself to the OS as a non-disk device type, although its true identity is known by the multipath driver.

Abstract: A search engine apparatus having a built-in functional test may include an input generator, a search engine, a pseudo search engine and a comparator. The inputs generator is suitable for generating outputs including commands and points associated with the commands. The search engine and the pseudo search engine are communicatively coupled to the inputs generator. The search engine suitable for performing search and edit operations and the pseudo search engine is suitable for simulating the search engine by generating pseudo search engine outputs. The comparator is communicatively coupled to the search engine and the pseudo search engine, and is suitable for comparing outputs received from the search engine and pseudo search engine.

Abstract: The present invention is directed to a method and apparatus of IC implementation based on a C++ language description. In an exemplary aspect of the present invention, a method for evaluating a C++ description by an IC includes the following steps. First, a C++ description including a C++ program is provided. Then, the C++ program is stored in a first memory module (e.g., a ROM, or the like) of an IC. Next, a scalar input and/or an input array may be provided to the IC. Then, the C++ program may be executed by a control device module of the IC. Next, a scalar output and/or an output array may be read from the IC.

Abstract: A method for providing online raid migration without non-volatile memory employs reconstruction of the RAID drives. In this manner, the method of the present invention protects online migration of data from power failure with little or no performance loss so that data can be recovered if power fails while migration is in progress, and migration may be resumed without the use of non-volatile memory.

Abstract: The present invention is directed to an advanced storage controller that is capable of providing parallel processing capabilities to a host processing system connected storage system to increase performance, functionality and reliability of the entire computing system. The advanced storage controller comprises at least one input interface and at least one output interface, a host device simulation component, a cache device component, a physical device component and a management component. Such an advanced storage controller further, includes one or more processor elements and storage elements, which may be shared by the components or dedicated to one component. Additionally, the advanced storage controller is scalable by the static or dynamic addition of components, processors and/or memory.

Abstract: A method and system which uses the method maintains data integrity during file transfers from a local drive medium to a RAID controller flash memory. A signature is added to the data file in the local drive by a utility program. The signature is multibyte and, preferably, is either four or eight bytes long. The RAID controller is loaded with software that traverses the data file until the signature is found. The RAID controller software discards the signature and any after patched data and stores the stripped off data into its flash memory. The utility program overcomes potential incompatibility between the file transfer protocol and a terminal emulation program.

Abstract: The present invention is directed to a system and method of cache management for storage controllers. In an aspect of the present invention, a system for storing electronic data may include a host and a data storage apparatus communicatively coupled to the host. The host has cache coherency functionality. The data storage apparatus includes a first storage controller communicatively coupled to at least one storage device, the first storage controller further coupled to a first cache. A second storage controller is also included, which is communicatively coupled to at least one storage device, the second storage controller further coupled to a second cache. The cache coherency functionality of the host provides coherency of the first cache coupled to the first storage controller with the second cache coupled to the second storage controller.

Abstract: The present invention is directed to a method and system for providing, a host input/output (I/O) module, a controller and application specific integrated circuit (ASIC) for utilization in transparent switched fabric data storage transport. The system implements I/O modules capable of translating between communication protocols for providing common message passing multi-channel data transport for data storage while providing apparent I/O circuit exclusivity to controllers. Implementing the system of the present invention allows for a common data transport system permitting component scalability and virtualization.

Abstract: A system, method and apparatus for providing and utilizing a storage cache descriptor by a storage controller are disclosed which provide the ability to effectively balance the size of storage controller cache blocks and the amount of data transferred in anticipation of requests, such as requests by a host. The apparatus may include a storage device, a storage controller and a cache. The storage controller stores electronic data in the cache by including a cache descriptor that defines data contained in a cache block, the cache descriptor including at least one field describing a device block of the cache block. The at least one field may include, by way of example, at least one of a present field, modified field, pinned field and write-in progress field.

Abstract: A method for populating and depopulating components of negligible impedance facilitates the testing of circuit boards. The test circuitry may be formed upon the circuit board under test. Testing may be performed with great accuracy for the time between the triggering edge of a clock pulse and a resulting valid signal change. Slew rates of bus signals may be more easily measured.

Abstract: An inductor-capacitor voltage controlled oscillator is implemented using an active inductor. The active inductor may use bipolar technology or CMOS technology. The VCO with an active inductor offers a more compact design and is useable with flip chip technology. The active inductor may be implemented in bipolar junction or complementary metal oxide semiconductor technology. The configuration of the voltage controlled oscillator with an active inductor of the present invention is fully differential and fully symmetric.

Abstract: The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a method for mapping platform-based design to multiple foundry processes may include the following steps. First, a virtual process is defined to include at least one fabrication process. A virtual process is a totality of variables associated with the population of candidate processes and any other process of interest, which might be purely hypothetical, that would be capable, in principle, of accommodating some or all slices. A virtual process may or may not be realized and is an abstract logical container for a population of processes. Then, the virtual process may be stored into a database. The virtual process may be in a representation including a list of attributes of entities making up the fabrication process. Next, optimization of the database may be performed using mathematical and statistical tools.

Abstract: The present invention is directed to an apparatus for providing convenient control of a power tool electrical system. A switch assembly of the present invention includes a first actuator and a second actuator, which is disposed remotely from the switch and first actuator. The second actuator is connected via a coupling device, such that user manipulation of either the first or second actuator is capable of controlling electricity flowing to the motor. Including a second actuator may permit the user to retain greater control over the tool when turning the power on or off. In additional exemplary aspects, a coupling device included in the switch assembly is configured and arranged so as to prevent inadvertent damage to the power tool such as by accidental engagement of a shaft lock while the motor is operating.

Abstract: The present invention is directed to a train detection system for detecting the velocity, presence, and direction of a railroad car which may be utilized in existing railroad crossing installations. The train detection system is suitable for self-testing of its components and if an anomaly has been detected, the train detection system is capable of placing the system in a fail-safe state. The train detection system of the present invention is also capable of constant communication between the sensor of said system and the implementing device of the train detection system via a wireless link.

Abstract: The present invention is an apparatus and system for providing a high quality spiral inductor in an integrated circuit environment. A layer of inductor may be placed within the metal layers along with negative capacitance generation circuitry of the present invention to compensate for the capacitance associated with the metal layers adjacent to the inductor to provide a higher quality factor for the inductor. Advantageously, circuitry of the present invention may be employed within an integrated circuit without modifying the layer structure of the integrated circuit. Additionally, values of the components of the circuitry may be selectively and independently chosen to synthesize a variable range of negative capacitance.

Abstract: The present invention is directed to a method and apparatus for mapping a customer memory onto a plurality of physical memories.

Abstract: The present invention is directed to a method for generating a tech-library for a logic function. A logic function has many representations. For each representation, a circuit for realizing the representation is decomposed into a combination of instances. An instance is a component logic circuit of a general logic circuit. There are pre-created tech-libraries for the instances. For example, a pre-created tech-library is created by categorizing tech-descriptions for primitive physical circuits based on a negation index. Thus, tech-descriptions for a circuit for realizing a representation are calculated from a combination of elements of the pre-created tech-libraries. Each calculated tech-description is compared with each existing element of a tech-library for the logic function. When a calculated tech-description has at least one marked parameter better or smaller than that of all existing elements of the tech-library for the logic function, the calculated tech-description is added to the tech-library.

Abstract: A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.

Abstract: The present invention is directed to platform architecture used for integrated circuit design. A system for providing distributed dynamic functionality in an electronic environment may include a plurality of platforms. The platforms are suitable for providing a logic function, and include embedded programmable logic, memory and a reconfigurable core. The logic, memory and reconfigurable core are communicatively coupled via a fabric interconnect. A map is also included which expresses logic functions of the plurality of platforms.