Abstract: A DRAM memory cell array includes a wiring layer formed at a storage-capacitor level of the cell for establishing a flipped connection of complementary bit lines, or for connecting support circuits in a DRAM cell array. The wiring layer includes a lower capacitor electrode and upper capacitor electrode which are formed simultaneously with respective plates of a storage capacitor. Both capacitor electrodes may be used to form distinct interconnections within a DRAM cell array.

Abstract: A monitor for electrically testing energy beam dose or focus of a layer formed on a substrate by lithographic processing. The monitor comprises a substrate having in a lithographically formed layer an array of electrically conductive elements comprising a plurality of spaced, substantially parallel elements having a length and a width, with the individual elements being electrically connected, and the lengths of the elements being sensitive to dose and focus of an energy beam in lithographically forming the layer. The monitor further includes at least one pad electrically connected to the array to apply current through the array elements. Upon applying a voltage across the array elements, the suitability of dose or focus of the lithographically formed layer may be determined by the resistance of the array. Preferably, ends of the individual elements are aligned along essentially straight lines to form an array edge.

Abstract: A method for reducing lens aberrations sensitivity and proximity effects of alternating phase shifted masks is described. The critical features of a chip design layout are first identified. Multiple, narrow phase regions and auxiliary phase transitions, which provide additional opaque features, are then formed alongside the critical features such that a grating pattern of substantially uniform pitch is printed. Together with a complementary trim mask, the circuit pattern so delineated has reduced sensitivity to lens aberrations and proximity effects.

Abstract: A method of forming a semiconductor structure having features of differing sizes, includes forming a first layer on a semiconductor substrate; patterning only a first plurality of features of a first feature size on the first layer; removing portions of the first layer, the portions corresponding to the first plurality of features, filling the first plurality of openings; forming a second layer, the second layer overlying the first layer and the filled openings; patterning a second plurality of features of a second feature size on the second layer; removing portions of the first layer and second layer, the portions corresponding to the second plurality of features, the second plurality of openings extending through the first and second layers, and filling the second plurality openings.

Abstract: In-line thickness measurement of a dielectric film layer on a surface of a workpiece subsequent to a polishing on a chemical-mechanical polishing machine in a polishing slurry is disclosed. The workpiece includes a given level of back-end-of-line (BEOL) structure including junctions. The measurement apparatus includes a platen and an electrode embedded within the platen. A positioning mechanism positions the workpiece above the electrode with the dielectric layer facing in a direction of the electrode. A slurry dam is used for maintaining a prescribed level of a conductive polishing slurry above the electrode, the prescribed level to ensure a desired slurry coverage of the workpiece. A capacitance sensor senses a system capacitance C in accordance with an RC equivalent circuit model, wherein the RC equivalent circuit includes a resistance R representative of the slurry and workpiece resistances and the system capacitance C representative of the dielectric material and junction capacitances.

Abstract: A planarizing method involves a first polishing step in which a relatively hard, low compressibility pad removes excess material of a first layer and planarizes the first layer. Deep defects emanating from the polishing surface formed during the first polishing step are then enlarged and filled with a second layer. After filling, and optionally annealing, the second layer is planarized by polishing with a relatively soft and high compressibility pad or by anisotropic etching.

Abstract: An charged particle beam imaging system reduces aberrations affecting resolution at the workpiece where the aberrations are caused by interactions between the charged particles in the beam. The average distance between the particles at a crossover image in the illumination subsystem is increased by positioning an annular aperture at the crossover image.

Abstract: Disclosed is a data transfer system that effectively reduces EMI radiation, in a device wherein EMI radiation very easily occurs, without the need for filters, etc. A system for transmitting data across a bus having a plurality of data lines includes a modulating circuit for modulating data so as to reduce the EMI radiation attributable to the data lines and a demodulating circuit for restoring the original data after transmission.

Abstract: Disclosed is a data transfer system that effectively reduces EMI radiation, in a device wherein EMI radiation very easily occurs, without the need for filters, etc. A system for transmitting data across a bus having a plurality of data lines includes a modulating circuit for modulating data so as to reduce the EMI radiation attributable to the data lines and a demodulating circuit for restoring the original data after transmission.

Abstract: Disclosed is an integrated circuit configuration including a carrier having recesses for supporting individual semiconductor die units. The semiconductor die units and the carrier recesses have lithographically defined dimensions so as to enable precise alignment and a high level of integration.

Abstract: A probe, a method of making the same, and a manner of using the same, suitable for "Metal-Oxide-Semiconductor (MOS) like" electrical characterization measurements on semiconductor substrates having overlying dielectric layers is disclosed. The probe comprises an electrically conductive probe needle, the needle having a rounded tip end of a first radius, the rounded tip end further being suitable for undergoing a plastic deformation. The needle is positioned above the dielectric layer on the semiconductor substrate and the needle tip forced down onto the smooth surface of the dielectric layer in a controlled manner for causing the needle tip to undergo a plastic deformation in which an outer portion of the rounded tip end is maintained at the first radius and an inner portion of the rounded tip end is increased to a second radius, the second radius being larger than the first.

Abstract: An apparatus for use with a computer system for identifying dependencies within a register, which dependencies are established by a succession of instructions for the computer system. The register includes a plurality of cells which may be in a hierarchical arrangement of register storage sets. In its preferred embodiment, the apparatus comprises a storage means for storing a bit map, which bit map is configured to provide bit map identifications identifying designated register storage sets. The bit map represents the hierarchical arrangement. The apparatus further comprises a logic means for logically treating information, which logic means is coupled with the storage means and with the computer system. The logic means receives a first bit map identification from a first instruction (the first bit map identification identifies a first register storage set), and receives a second bit map identification from a second instruction (the second bit map identification identifies a second register storage set.

Abstract: A programmable logic circuit provides a variety of logic functions including AND/NAND, OR/NOR, XOR/XNOR. Selection of logic function is provided by controlling inputs, using programmable inverters and programmable multiplexers. The logic circuit can be incorporated into a field programmable gate array.

Abstract: A multi-station Step and Repeat Apparatus (Stepper) for imaging semiconductor wafers. The stepper has at least 2 stations, at least one of which is for imaging. The second station may be used for image field characterization, or image defect correction, or for Phase Shift Mask (PSM) loop cutting. Multiple laser beams directed in orthogonal directions provide interferometric monitoring to track wafer locations for wafers on the stepper.

Abstract: A method and apparatus for a computer graphics system identifies the format of video pixel data in a data stream having a plurality of data formats including a first pixel data format and a second pixel data format, the second pixel data format being a YUV format. The method comprises the steps of (a) receiving pixel data; (b) selecting an output channel in response to at least one particular value of at least one bit of each received pixel datum wherein the particular value identifies the data format as either the first pixel data format or the YUV format; and (c) providing the pixel data to the selected output channel. Also provided is a circuit in a video graphics controller and a computer system having such circuit according to the method.

Abstract: A vertical double-gate field effect transistor includes a source layer, an epitaxial channel layer and a drain layer arranged in a stack on a bulk or SOI substrate. The gate oxide is thermally grown on the sides of the stack using differential oxidation rates to minimize input capacitance problems. The gate wraps around one end of the stack, while contacts are formed on a second end. An etch-stop layer embedded in the second end of the stack enables contact to be made directly to the channel layer.

Abstract: A nanolithographic method for forming fine features is disclosed. A carrier layer, such as a photoresist, is deposited on a substrate. A relatively large pattern is imposed on the carrier layer by means of conventional photolithographic methods. The carrier layer is then exposed to a maskless etch, such as by ashing in oxygen, such that non-volatile materials within the carrier layer aggregate along the center line of the pattern, forming a residual pattern of significantly reduced width when compared to the original carrier layer pattern.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: A globally distributed system clock is received and selectively gated by local clock generators responsive to global control signals. The local clock generators, which are located proximately to sequential circuits having serial scan paths, produce scan and functional clock signals adapted to the sequential circuits, which may have a variety of required timing diagrams.

Abstract: An improved storage system for use with computers. The system includes a memory array bifurcated into a first and second array segment and a differential sense amplifier configured for selective operation in a first mode establishing one array segment as a reference load and the other array segment as a dynamic load, and a second mode establishing the other array segment as a reference load and the one array segment as a dynamic load. The amplifier senses changes in a parameter in the dynamic load with respect to the reference load.