Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: A method of gettering an SOI wafer from the front side of the wafer includes depositing a gettering layer, such as polysilicon, on the SOI layer and annealing the SOI wafer with the gettering layer in place. A polish stop structure, which can be deposited before or after the gettering layer, provides a means for selectively removing the gettering layer from the SOI wafer without damaging the surface or eroding the thickness of the SOI layer.

Abstract: Disclosed is an improved push-pull off-chip driver circuit. The circuit includes a push-pull amplifier including a pull-up transistor and a pull-down transistor, each provided with independent inputs and connected at the output node. The input to the pull-up transistor is provided by a transmission gate having an n-channel transistor connected in parallel with a p-channel transistor. A control transistor is coupled between the output node and the gate of the pull-up transistor to provide a protective bias. A feedback override circuit is coupled between the output node and the gate of the p-channel transmission gate transistor to selectively provide either Vout or a low level potential to that gate. The feedback override circuit improves the response time and noise immunity of a prior art off-chip driver in the active mode in a manner consistent with the objectives of protecting the gate oxides from high voltage stress and prevent leakage currents during the high-impedance mode.

Abstract: A laser ablation mask and a method of fabrication therefor. The mask has a pattern of clear areas and scattering areas. The scattering areas are covered with randomly formed facets. The facets act as scattering centers. Areas clear of facets transmit laser energy. Scattering areas refract laser energy. Laser energy directed at the mask, will pass through the clear mask areas to selectively ablate an organic layer placed opposite the mask. However, laser energy is scattered when striking and passing through the scattering areas such that insufficient laser energy passes directly through the mask to reach the organic layer for ablation to occur. The mask is formed by depositing and patterning a metal mask layer on a quartz plate. The patterned mask layer protects intended clear areas. Scattering areas are formed in unprotected plate areas by subjecting the plate to a polymethacrylic acid/bifluoride solution.

Abstract: The preferred embodiment of the present invention is a method of enhancing normally unenhanced features types. Pattern shapes are placed on two or more relatively simple, modified masks instead of using a single mask containing diverse feature types. On these modified masks, (hereinafter "overlay masks"), all of the features are the type normally enhanced. A composite pattern is printed into photoresist through successive exposure to the overlay masks.

Abstract: An ultrasonic jet semiconductor wafer cleaning method and apparatus for removing debris from a surface of a semiconductor wafer as the wafer is rotated about a prescribed axis in a cleaning plane whereby a housing having a principal axis, an inlet port, and an outlet port is provided. The method further includes producing focused ultrasonic waves of acoustic energy concentric with and incident the outlet port to form a jet stream of cleaning liquid released through the outlet port; adjustably positioning a focal point of the focused ultrasonic waves between a first focal point position and a second focal point position along an axis; and sweeping the housing in an reciprocating manner along a sweep path.

Abstract: A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pair of adjacent memory array cells associated with the bit line. In one embodiment, multiple layers of polysilicon are utilized to form a control gate, a floating gate, a source and a drain. In another embodiment, multiple layers of polysilicon are utilized to form an auxiliary gate, a floating gate, a source and a drain. In both embodiments, the polysilicon layers self-aligned to substantially reduce polysilicon layer-overlap so as to minimize parasitic capacitances. Domino and Skippy Domino schemes are used to program and read the memory array cells.

Abstract: A method and circuit for store rounding a number wherein the guard bit and least significant bit of the number are selectively exchanged depending on the IEEE rounding mode to simplify the decision-making circuit. Zero detection logic is performed on the guard, round and sticky bit positions to determine if incrementing is required. An incrementer provided with the number and a guard bit, which may be the true guard bit or a predetermined constant value depending on the rounding mode, responds to the zero detection logic to increment the number from the guard bit position.

Abstract: A probe, a method of making the same, and a manner of using the same, suitable for "Metal-Oxide-Semiconductor (MOS) like" electrical characterization measurements on semiconductor substrates having overlying dielectric layers is disclosed. The probe comprises an electrically conductive probe needle, the needle having a rounded tip end of a first radius, the rounded tip end further being suitable for undergoing a plastic deformation. The needle is positioned above the dielectric layer on the semiconductor substrate and the needle tip forced down onto the smooth surface of the dielectric layer in a controlled manner for causing the needle tip to undergo a plastic deformation in which an outer portion of the rounded tip end is maintained at the first radius and an inner portion of the rounded tip end is increased to a second radius, the second radius being larger than the first.

Abstract: A method and apparatus comprises heating a wafer to a temperature sufficient to temperature stress the wafer and enable ion motion. The wafer is then initialized in a measurement region with a non-contact corona discharge of a first polarity until a first dielectric field is developed, wherein any mobile ions present in the dielectric layer or at an air/dielectric interface move to a substrate/dielectric interface. A non-contact pulsed corona discharge of a second polarity, opposite the first polarity, is then applied to the wafer until a second dielectric field is developed and an amount of corona discharge Q.sub.MEASURED necessary to change the dielectric field from the first dielectric field to the second dielectric field is measured, wherein any mobile ions present at the dielectric/substrate interface move to the air/dielectric interface. An ideal amount of corona discharge Q.sub.

Abstract: A contactless sheet resistance measurement apparatus and a method for measuring the sheet resistance of a desired layer of a first conductivity type, formed upon a substrate of an opposite conductivity type, is disclosed. The apparatus comprises a junction capacitance establishing means, a point location alternating current AC photovoltage generating means for generating a laterally propagated AC photovoltage, an attenuation and phase shift monitoring means for monitoring the .laterally propagated AC photovoltage, and a sheet resistance signal generating means responsive to the-junction capacitance establishing means, the AC photovoltage generating means, and the attenuation and phase shift monitoring means for generating an output signal indicative of a sheet resistance R.sub.S of the desired layer according to a prescribed sheet resistance model.

Abstract: The method of the present invention is particularly directed to plastic packaged modules of the type wherein the contact zones of the chip are connected by wire-bonding to lead conductors and wherein the chip is molded in etch resistant resins. The opening method includes the steps of: a) polishing the module topside to eliminate the top part of the plastic encapsulating resin until the conductors of the lead frame are exposed; b) removing the lead frame; c) roughly polishing the module backside to eliminate the bottom part of the plastic encapsulating resin until the passive face of the silicon chip is exposed; d) immersing the resulting module in a hot fuming nitric acid bath raised to a temperature of about 120.degree. C.