Abstract: The frequency of a signal is classified in at least two nonoverlapping frequency ranges using the variable frequency of a clock signal as a reference. The clock signal is applied to the count input of a first up counter, and the signal to the reset input of this up counter and to the enable input of a first buffer. The parallel inputs of the first buffer are connected to the count outputs of the up counter, and the parallel outputs of this buffer are coupled to the parallel inputs of a multiple comparator in which each nonoverlapping frequency range is assigned a digital output. Each of these digital outputs is connected to the D input of a D flip-flop, which is clocked by the signal, and to one of the two inputs of an EXOR gate having its other input connected to the Q output of the associated flip-flop.

Abstract: In an integrated matrix of nonvolatile, reprogrammable storage cells, additional memory is provided to replace defective rows of storage cells. The addresses of the defective rows are stored in a region of the matrix. A correction register can be loaded with the addresses of the defective rows from the region of the matrix when power is first applied to the matrix or whenever the applied power deviates from the expected, nominal value.

Abstract: A data reduction circuit employs a differential pulse code modulator for input video signals where the time-critical loop includes a loop subtractor (s2), a quantizer (q), and a loop delay element (v3), so that differential pulse code modulation can be performed at higher clock rates than with conventional architectures. With 2 .mu.m CMOS or N-channel MOS technology, for example, clock rates of 17 to 20 MHz are possible. The circuit includes a limiter circuit which applies the input video signals to the loop subtractor minuend input after processing the same. The output of the delay element in the loop is applied to inputs of a first adder, a vertical predictor and a constant multiplier, the multiplier receive a weighting factor equal to the square of a given weighting factor with the output of the multiplier applied to the subtrahend input of a first subtractor whose output is coupled to the input of the loop subtractor via a delay element.

Abstract: A system is provided for forming an end of an optical fiber into a lens, which produces a lensed fiber having an especially smooth lens surface and high strength near the intersection of the lens and the rest of the fiber. A lens is formed by establishing a pair of electrodes on opposite sides of a fiber end portion and establishing an arc between the electrode tips for a sufficient current and time to melt the fiber end portion into a lens, with the arc being repeatedly terminated and restarted at a rate of thousands of times per second.

Abstract: The circuit merely comprises three transistors, namely one transfer transistor (t) arranged between the input (e) and the output (a), a load transistor (l) connected as a resistor, and a clamping transistor (k), with both of the latter connecting the output (a) to the source of operating voltage (U). The interconnected gates of both the clamping and the transfer transistor (k, t) are connected to a source of reference voltage (Ur). If these two transistors (k, t) are of the depletion type, the two gates thereof may be connected to the zero point of the circuit. The circuit is particularly quick and simple.

Abstract: A test adapter is provided for connection to a PLCC (Plastic Leaded Clip Carrier), hereinafter referred to as a carrier, which assures accurate alignment with the carrier, which can be locked to the carrier during a test, which has a width only slightly greater than that of the carrier to enable testing of closely mounted carriers, and which can be simply constructed. The adapter includes an inner housing that bears against the top of the carrier and four contact frames pivotally mounted on the housing and carrying contacts that engage leads of the carrier. Each contact frame has separators between the contacts, the separators passing between the leads of the carrier to directly engage the sides of the carrier housing. The lower surface portions of the separators are slightly angled from the vertical so when they press against angled surfaces on the carrier housing sides, the adapter is locked to the carrier.

Abstract: The circuit arrangement includes a basic circuit for calculating the zeroth approximation and expandable by at least one correction circuit for calculating a first or further approximations. The basic circuit contains a first adder, a second adder, a first constant multiplier, a second constant multiplier, a first absolute-value stage, a second absolute-value stage and a third absolute-value stage which is interposed between a subtracter and the input of the second constant multiplier. The output of the second constant multiplier is coupled to one input of the second adder, whose output provides the zeroth approximation to the value of the complex digital quantity. Each of the two input signals is fed through one of the absolute-value stages to one of the two inputs of the subtracter and the first adder.

Abstract: A CMOS inverter chain includes the alternating series connection of N- and P-inverters. An N-inverter is a conventional type of CMOS inverter employing an N-intermediate transistor between both the P- and the N-transistor; a P-inverter, however, is a CMOS inverter employing a P-intermediate transistor between both the P- and the N-transistor. The gates of the intermediate transistors are interconnected and controlled by the clock signal, whereas the inverter input is constituted by the interconnected gates of the P- and the N-transistor of each inverter. Such an inverter chain can be used, for example, as a digital pulse width discriminator, as a final position counter, as a circuit for compensating signal drop-outs in input pulses, or else for effecting ring oscillator synchronizations.

Abstract: An integrated memory system includes a microcomputer which, at defined intervals and by employing a classifying circuit integrated in an EEPROM, checks the memory cells of the EEPROM with respect to variations of the threshold values. Upon detection of a fault in a row or column which has thus been recognized as being faulty, this faulty row or column whose address is then stored in one EEPROM area, is replaced by a redundant row or column in another area by making use of a correction register.

Abstract: A cellular array processor chip includes a common bus communicating with the individual cells thereof. The common bus can be monitored during chip testing to detect the presence, or absence, of a defective cell. Each cell can be inactivated with respect to the common bus. During testing if the presence of a defective cell is determined to exist each cell is individually tested until a defective cell is located. That cell is inactivated and the chip testing is resumed until all defective cells are located and inactivated.

Abstract: This circuit arrangement is designed for use in digital color-television receivers or the like and contains for each of the two digital color-difference signals a slope detector to which both a digital signal defining an amplitude threshold value and a digital signal defining a time threshold value are applied. At least one intermediate value occurring during an edge to be steepened is stored, and at the same time value of the steepened edge, it is "inserted" into the latter. This is done by means of memories switches, output registers, and a sequence controller.

Abstract: The output signal of one tuner or of other TV signal sources in the base band are digitized and stored in a part of a memory. After automatic switching over to another TV-channel, this new signal is stored in another part of the memory and so on. The whole memory is then read out continuously and produces the displayed multipicture on the screen.

Abstract: A dielectric composition comprising a base of non-stoichiometric lead magnesium niobate, non-stoichiometric lead zinc niobate, lead zirconate, titanium dioxide and bismuth titanate, together with a further oxide additive, in particular nickel oxide, manganese oxide, cobalt oxide or a rare earth, has a low firing temperature (900.degree.-1000.degree. C.), high dielectric constant (up to 14,750), low tan .delta.(<2.5% at 20.degree. C.) and Z5U temperature coefficient of capacitance.

Abstract: A system for dispensing components one-at-a-time upon demand for utilization comprises a component handling assembly and a buffer assembly. The component handling assembly receives bulk quantities of the components and when activated, properly orients each component and supplies the components in a randomly timed sequence to the buffer assembly. The buffer assembly comprises a cylindrical upper receiving housing having a plurality of cylindrical through-chambers radially disposed in a circular pattern and rotatable about a central generally vertical axis. A cylindrical lower dispensing member is closely aligned and coaxially rotatable both independently and together with the receiving housing. The dispensing member has a planar upper surface which forms a bottom cover for the chambers in the upper receiving housing and has a single passageway that can be aligned with each of the upper receiving chambers to dispense a component.

Abstract: To determine the phase difference between the edge of a pulse of a first clock signal and the edge of a pulse of a second clock signal with an integrable phase meter circuit, the second clock signal is fed through a frequency-divider circuit to the input of an unclocked delay line including m delay elements, and to a second register containing m cells, while the m cells of a first register are clocked by the first clock signal. The outputs of the kth register cells are compared in the kth XOR gate of a row of m XOR gates, so that, when the levels of these outputs are unlike, a logic 1 appears at the output of the kth gate. The phase is obtained at the n-bit output of a multiple adder adding the logic levels, the accuracy corresponding to m, which is preferably equal to 2.sup.n.

Abstract: An array reconfiguration apparatus is employed in large integrated circuits and large systems. The apparatus makes use of spare wires and/or computation elements which are incorporated in the array. The apparatus uses spare wires in place of defective wires and/or the apparatus uses spare computation elements in place of defective computation elements so that an operational system may be created in spite of the occurrence of numerous manufacturing or lifetime faults. The excess wires are utilized as data input and output lines and as such each data line is associated with a bidirectional buffer/receiver (B/R). The bidirectional B/R's are capable of transmitting data in either direction as from an input terminal to an output terminal or vice versa. Each data line is connected to a bidirectional multiplexing device which has a control input. Control logic means has dynamically stored therein the assignment of each significant wire and each computation element.

Abstract: A fixture is provided which enables the rapid mounting of an optical fiber contact with its forward end at a predetermined position and orientation with respect to arc-creating electrodes. The fixture includes a frame with a vertical slot having a width greater than the diameter of the cylindrical contact, and a plurality of spring-biased plungers which enable the contact to be pushed sidewardly into the slot and which thereafter press the contact against the slot bottom. The contact can slide vertically along the slot and plungers until a stop on the contact abuts a corresponding stop on the fixture and an orienting pin on the fixture passes into a corresponding hole in the contact stop.

Abstract: In this circuit, the subcircuits substantially contributing to the computation time of the time-critical loop are only a subtracter, a quantizer and a delay element. The digital video signals whose number of bits is to be reduced can thus have clock rates of 17 to 20 MHz if the circuit is implemented using CMOS or N-channel MOS technology.

Abstract: An optic fiber contact assembly is described, which can be installed in a contact hole of a connector housing that was designed for holding front release electrical contacts. The assembly includes a central tube which holds the end of an optical fiber, an outer sleeve which surrounds the tube and which fits within the contact hole and is held by a front release clip therein, and a coil spring lying between the front ends of the tube and sleeve for biasing the tube forwardly. A guide sleeve clips onto the front of the tube, so the spring can be compressed between the rear end of the guide sleeve and a shoulder on the outer sleeve. The spring is pre-loaded by a clip which lies between the rear end of the outer sleeve and a shoulder formed on the rear end of the tube.

Abstract: An apparatus is provided for use in molding a ferrule which must hold an optical fiber cable so the optical fiber lies precisely concentric with the cylindrical outside surface of the forward portion of the ferrule. A corepin which lies within a mold to form a ferrule cavity between them, has a rearward end held to the mold and a forward end which must be held precisely concentric with the inside surface of the ferrule cavity. A bushing of clover leaf design is positioned in the mold cavity, and has three radially-extending arms that precisely center the forward end of the corepin, while leaving spaces between the arms through which plastic can flow during the molding of the ferrule. The radially-outer arms of the bushing are tied by tying portions whose radially inside surfaces form an interrupted cylindrical outside surface of the ferrule.