Abstract: A method and apparatus for bridging network protocols is disclosed. In one embodiment, a data frame is received and stored in a dual-port memory queue by hardware logic. An embedded processor is notified of the data frame once a programmable number of bytes of the data frame have been received and stored. Once notified, the embedded processor may then undertake to read the data frame from the memory queue while the hardware logic is still writing to the memory queue. In one embodiment, the processor may then translate the data frame's protocol and begin transmitting it out over a network connection, all while the data frame's payload is still being received.

Abstract: The invention in one variation is a modular recovery apparatus for dispensing a tether spool having a tow line with a float, where the tow line can be used to retrieve an unmanned underwater vehicle and other underwater platforms. The modular recovery apparatus can be triggered underwater or on the surface, and being modular in configuration it is suitable to be fitted to a variety of unmanned underwater vehicles (UUVs). The apparatus has a tether spool that is spring loaded, such that when the tether spool is deployed, the spring expels the tether spool with sufficient force to clearly separate it from the UUV. One end of the tow line is typically fastened to a tow point on the UUV, and an opposing end is attached to the float. When the tether spool is deployed, the tow line unwinds from the float, providing a securable length.

Abstract: Devices, systems, methods, and other embodiments associated with magnetic resonance imaging (MRI) are described. In one embodiment, an apparatus includes an RF coil for use in multi-nuclear excitation in magnetic resonance imaging (MRI). The RF coil includes a set of two or more L-C coils. Members of the set of two or more L-C coils have individual resonance frequencies. An RF amplifier is placed near the RF coil. The RF amplifier is controllable to selectively produce the individual resonance frequency of a member of the set of two or more L-C coils based, at least in part, on a digital input provided to the RF amplifier.

Abstract: Feedback circuits with DC offset cancellation are described. In an exemplary design, a feedback circuit includes a slow integrator and a summer. The slow integrator receives a first intermediate signal at a particular point in the feedback circuit and provides a second intermediate signal. The summer is located after the particular point and receives and sums the first and second intermediate signals to reduce DC offset in the first intermediate signal. In one design, the feedback circuit may be a delta-sigma (??) modulator with at least one integrator coupled in cascade. The slow integrator is coupled to the output of the last integrator, receives the first intermediate signal from the last integrator, and provides the second intermediate signal. The summer is coupled to the last integrator and the slow integrator and sums the first and second intermediate signals to reduce DC offset in the first intermediate signal.

Abstract: A resistance calibration code generating apparatus includes a code calibration unit configured to calibrate and output code values of a resistance calibration code during predetermined cycles of a calibration clock, which are determined by a code calibration time control command, and a calibration clock generating unit configured to output the calibration clock using a code calibration command.

Abstract: Systems methods, and other embodiments associated with acquiring intersecting TrueFISP images using grouped reverse centric phase encoding are described. One example method includes controlling an MRI apparatus to produce a TrueFISP sequence that delays acquisition of the center of k-space to reduce saturation banding artifacts. The example method also includes controlling the MRI apparatus to produce a TrueFISP sequence that reduces eddy current artifacts by grouping (e.g., pairing) lines in k-space. The method concludes by acquiring NMR signal in response to the TrueFISP sequence.

Abstract: A driver amplifier in an integrated circuit is suitable for driving a signal onto an output node and through an output terminal, and through a matching network to a power amplifier. A novel Programmable Output Impedance Adjustment Circuit (POIAC) within the integrated circuit is coupled to the output node and affects an output impedance looking into the output terminal. When the output impedance would otherwise change (for example, due to a driver amplifier power gain change), the POIAC adjusts how it loads the output node such that the output impedance remains substantially constant. The POIAC uses a series-connected inductor and capacitor L-C-R circuit to load the output node, thereby reducing the amount of capacitance and die area required to perform multi-band impedance matching with a power amplifier. Multi-band operation is accomplished by changing an effective capacitance in the L-C-R circuit depending on communication band information received by the POIAC.

Abstract: Disclosed are compositions comprising an inner core and at least two surrounding layers. The compositions are suitable for use in humans and other mammals, particularly wherein a component of the inner core is susceptible to moisture. The compositions comprise an inner core comprising one or more components; an inner layer which surrounds the inner core, wherein the inner layer is selected from continuous coatings insoluble at a pH of about 3 or less, continuous coatings having a coating weight of from about 3 mg/cm2, and combinations thereof; and an outer layer which surrounds the inner layer, wherein the outer layer is hydrophobic.

Abstract: A semiconductor memory device includes: a first strobe signal generation unit configured to generate a first rising strobe signal in response to a rising DLL clock signal; a second strobe signal generation unit configured to generate a second rising strobe signal in response to a falling DLL clock signal, the second rising strobe signal having an opposite phase to the first rising strobe signal and being activated at the same timing as the first rising strobe signal; a third strobe signal generation unit configured to generate a first falling strobe signal in response to the falling DLL clock signal; and a fourth strobe signal generation unit configured to generate a second falling strobe signal in response to the rising DLL clock signal, the second falling strobe signal having an opposite phase to the first falling strobe signal and being activated at the same timing as the first falling strobe signal.

Abstract: A multiple torpedo mine is capable of launching multiple torpedoes in water simultaneously or at predetermined intervals. The mine has an elongate container having multiple launch tubes with launch tube covers and each containing a torpedo. A programmable target detection sensor unit in the elongate container senses impinging stimuli indicative of an approaching target and generates representative target signals. A main controller in the elongate container is coupled to receive the target signals from the target detection sensor unit, and the main controller is preprogrammed to recognize targets of interest and generate appropriate launch control signals for the torpedoes. A launching system in the elongate container is coupled to the main controller and each of the launch tubes to feed high pressure gas to the base and interior of the launch tubes to launch the torpedoes into the water.

Abstract: A method of reducing startup time of an embedded system can include: instantiating a circuit, specified by a first circuit design, within an integrated circuit (IC), booting a first build of an operating system executed by a processor to a steady state, and responsive to achieving the steady state, storing a circuit operational state of the circuit instantiated within the IC, an operational state of the processor, and a state of an executable memory utilized by the processor. A second circuit design can be created and a second build of the operating system can be created that collectively specify the circuit operational state, the operational state of the processor, and a state of an executable memory. The second circuit design and the second build of the operating system can be stored in the memory.

Abstract: A method for fabricating a vertical channel type non-volatile memory device including forming a source region, alternately forming a plurality of interlayer dielectric layers and a plurality of conductive layers for a gate electrode over a substrate with the source region formed therein, forming a trench exposing the source region by etching the plurality of interlayer dielectric layers and the plurality of conductive layers for a gate electrode, and siliciding the conductive layers for a gate electrode and the source region that are exposed through the trench.

Abstract: An improved mat is disclosed. Long and short legs support the mat and cause it to feel resilient although it is fabricated from hard rubber. The mat has drain holes on vertical surfaces. Ribs prevent the mat from embedding within grating. Grit is selectively placed upon the mat and physically supported. Adhesive for bonding the grit is retained by retention lips. Also disclosed is a process for creating drain holes on vertical surfaces of mats by attaching a grooving tool to a robot and programming the robot to cut through molded mat channels to create the desired drain holes. An additional process uses the robot to selectively place adhesive upon the mat. An adhesive dispenser is attached to the robot and the robot is appropriately programmed.

Abstract: A method and apparatus is provided for the calculation of maverick control limits. The maverick control limit method selects the correct parameter(s) as critical parameters to be utilized by the maverick control limit method. Next, the maverick control limit method identifies the probability density function that is associated with the parametric data set(s) that are associated with the critical parameter(s). Next, abnormal data points within the measured parametric data set(s) are removed. Maverick control limits are then calculated to properly disposition semiconductor die into pass/fail categories.

Abstract: The present invention provides humanized anti-human IFN-? monoclonal antibodies useful for therapeutic applications in humans. Preferred antibodies are humanized versions of murine antibodies ACO-1 and ACO-2, as well as variants thereof.

Abstract: The present invention relates to a liquid composition, having a pH between 3 and 7, comprising a non ionic surfactant or a mixture thereof, an amine oxide or a mixture thereof, a glycol ether solvent, a chelant and a cationic polymer. The composition of the present invention does not contain any anionic surfactant. The present invention also encompasses a process of treating hard-surfaces, including delicate hard-surfaces located in bathrooms, wherein a liquid composition according to the present invention is applied onto said surfaces.

Abstract: A method of preparing a solid oxide fuel cell is described herein, as well as the fuel cell itself. The method comprises forming a cathode layer comprising a strontium composition on a ceramic electrolyte layer; and forming a barrier layer between the cathode layer and an overlying interconnect structure comprising chromium, so as to substantially prevent the formation of strontium chromate.

Abstract: The polishing pad is useful for polishing at least one of magnetic, optical and semiconductor substrates. A porous polishing layer includes a dual porosity structure within a polyurethane matrix. The dual porosity structure has a primary set of pores having pore walls with a thickness of 15 to 55 ?m and a storage modulus of 10 to 60 MPa measured at 25° C. In addition, pore walls contain a secondary set of pores having an average pore size of 5 to 30 ?m. The porous polishing layer is either fixed to a polymeric film or sheet substrate or formed into a woven or non-woven structure to form the polishing pad.

Abstract: An electrode assembly for a particulate matter sensor in a gas environment. The electrode assembly includes an insulating tube, a conductor, and a positioning structure. The insulating tube has an outer surface and defines an interior cavity with an interior surface. The conductor is disposed within the interior cavity of the insulating tube. The conductor is electrically coupled to an electrode at a first end of the insulating tube and includes a contact portion at a second end of the insulating tube for connection to an external conductor. The positioning structure is coupled to the conductor. The positioning structure mechanically supports the conductor at a distance from the interior surface of the insulating tube to at least partially define an air dielectric gap at approximately a heater location corresponding to a heater.