Patents Represented by Attorney T

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  • Non-lethal projectile for dispersing payload upon target impact
    Patent number: 8186275
    Abstract: A non-lethal projectile has an enclosed frangible shell with a nose assembly coupled thereto. The nose assembly is designed to be frangible and absorb shock energy incident on the nose assembly. Frangible containers disposed in the shell occupy a portion of the volume defined thereby such that spaces between the containers are defined. Each container is configured to divide into particles when the container fractures. Each container contains at least one payload material. A gelatinous carbomer fills the spaces between the containers.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: May 29, 2012
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Robert Woodall, Felipe Garcia, Greg Reitmeyer
  • Method and apparatus for organizing object geometry for spatial and memory coherency and optimal rendering
    Patent number: 8188999
    Abstract: Methods and computing devices enable the generation of contiguous triangle patches for use in generating triangle strips for processing in a computer graphics engine. A seed triangle is selected and a patch of contiguous triangles is formed by incrementally adding adjacent triangles to the patch at equal steps from the seed triangle until a limit is reached or no more triangles can be added to the patch. Triangles whose vertices are already included in the patch are also added to the patch. If no more triangles can be added to the patch before the vertex limit is reached, a new seed triangle may be selected and another patch generated until the vertex limit is reached. Forming patches of contiguous triangles before generating triangle strips improves memory utilization can speed the processing of computer graphic objects.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: May 29, 2012
    Assignee: QUALCOMM Incorporated
    Inventor: Angus MacDonald Dorbie
  • Methods and algorithms for cell enumeration in a low-cost cytometer
    Patent number: 8189899
    Abstract: The enumeration of cells in fluids by flow cytometry is widely used across many disciplines such as assessment of leukocyte subsets in different bodily fluids or of bacterial contamination in environmental samples, food products and bodily fluids. For many applications the cost, size and complexity of the instruments prevents wider use, for example, CD4 analysis in HIV monitoring in resource-poor countries. The novel device, methods and algorithms disclosed herein largely overcome these limitations. Briefly, all cells in a biological sample are fluorescently labeled, but only the target cells are also magnetically labeled. In addition, non-magnetically labeled cells are imaged for viability in a modified slide configuration. The labeled sample, in a chamber or cuvet, is placed between two wedge-shaped magnets to selectively move the magnetically labeled cells to the observation surface of the cuvet.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: May 29, 2012
    Assignee: Veridex, LLC
    Inventors: Frank A. W. Coumans, Jan Greve, Frank P. Modica, Leon W. M. M. Terstappen, Arjan G. J. Tibbe, John A. Verrant
  • Semiconductor memory device
    Patent number: 8189417
    Abstract: A semiconductor memory device uses a magnetic tunnel junction device (MTJ) and includes a memory cell connected between a first driving line and a second driving line and configured to store data having a data state that is determined based on a direction of a current flowing through the first and the second driving lines, and a current controlling block configured to control a supply current provided to the first and second driving lines in response to temperature information in a writing operation.
    Type: Grant
    Filed: July 22, 2011
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Young-Hoon Oh, Sung-Yeon Lee
  • Page buffer circuit of nonvolatile memory device and method of operating the same
    Patent number: 8189394
    Abstract: The page buffer of a nonvolatile memory device utilizing a double verification method using first and second verification voltages when performing a program verification operation includes a first latch unit including a first latch configured to store input data and results of a program operation and a first verification operation using the first verification voltage, and a second latch unit including a second latch configured to have a higher latch trip point than the first latch and to store a result of a second verification operation using the second verification voltage, which is less than the first verification voltage, when the first verification operation is performed.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun Jong Jin, Jin Haeng Lee
  • Method for fabricating semiconductor device
    Patent number: 8187952
    Abstract: A method for fabricating a semiconductor device includes etching a semiconductor substrate using a hard mask layer as a barrier to form a trench defining a plurality of active regions, forming a gap-fill layer to gap-fill a portion of the inside of the trench so that the hard mask layer becomes a protrusion, forming spacers covering both sides of the protrusion, removing one of the spacers using a doped etch barrier as an etch barrier, and etching the gap-fill layer using a remaining spacer as an etch barrier to form a side trench exposing one side of the active region.
    Type: Grant
    Filed: December 24, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Uk Kim, Sang-Oh Lee
  • Gooseneck trailer attachment assembly and center deck elevation system
    Patent number: 8186704
    Abstract: Taught herein is a trailer having a gooseneck that can be engaged with the fifth wheel of a road tractor, rear truck unit, and a detachable cargo deck connecting the gooseneck with the truck unit. The cargo deck may be detached from the gooseneck and rested on the ground to allow heavy equipment to be loaded onto the cargo deck. The cargo deck can be reattached to the gooseneck, and elevated and locked into any one of three positions, each substantially parallel with the road, by an elevating means in the gooseneck and the truck unit. Thus the trailer of the present invention can be configured to accommodate cargo have a wide range of weight and size.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: May 29, 2012
    Inventor: Anthony Cesternino
  • Integrated circuit
    Patent number: 8189308
    Abstract: An integrated circuit includes an input/output pad for signal exchange with an external circuit, an electrostatic discharge (ESD) protection unit coupled to the input/output pad and configured to form an ESD path between a first voltage line and a second voltage line, a first drive transistor coupled between the first voltage line and the input/output pad, a first driving control unit coupled to a gate of the first drive transistor and configured to control the first drive transistor, a first dummy drive transistor coupled between the first voltage line and the input/output pad, and a first auxiliary driving control unit configured to supply the first voltage to a gate of the first dummy drive transistor in a normal operation mode, and float the gate of the first dummy drive transistor in a non-operation mode in which no power is supplied.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Dong-Ju Lim
  • Page buffer circuit
    Patent number: 8189392
    Abstract: A page buffer circuit comprises a first sensing unit configured to sense a voltage of a bit line and change a voltage of a first sense node, a data conversion unit configured to sense a voltage level of the first sense node and change a voltage level of a second sense node or to couple the second sense node and the first sense node, and first and second latch units coupled in common to the second sense node.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Soo Park
  • Nonvolatile memory device for preventing a source line bouncing phenomenon
    Patent number: 8184482
    Abstract: A nonvolatile memory device includes a memory cell array configured to include cell strings coupled between respective bit lines and a source line, a unilateral element coupled to the source line, and a negative voltage generation unit coupled to the unilateral element and configured to generate a negative voltage.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: May 22, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Cheul Hee Koo
  • Nonvolatile memory device and method of programming the same
    Patent number: 8184483
    Abstract: A nonvolatile memory device includes a memory cell array, including a first memory cell group configured to store data and a second memory cell group configured to store operation information, including first and second program start voltages, a page buffer unit, including page buffers each configured to store program data for memory cells or store data read from the memory cells, and a control unit configured to, when a program operation is first performed after power is supplied, count a number of program pulses until a verification operation using a first verification voltage is a pass, compare the counted number and a first number of program pulses, select either the first or second program start voltages according to a result of the comparison, and control the program operation to be performed using the selected program start voltage until the power is off.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: May 22, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Seung Min Oh
  • Method and apparatus for an adaptive systolic array structure
    Patent number: 8184696
    Abstract: A method and apparatus for an adaptive systolic array structure is initially configured for motion estimation calculations and optionally reconfigured as the motion estimation algorithm progresses. A scheduling map of the processing element (PE) calculations for a given motion estimation algorithm is generated. A systolic array structure may then be generated from the scheduling map, whereby the size and shape of a processing element array is configured to generate the search pattern that is to be used during the search. In addition, delay elements may be implemented within the systolic array structure, so as to preserve the pixels of a current macroblock that are reused in accordance with the scheduling map. The systolic array structure may also be adapted by the motion estimation algorithm during subsequent search stages to accommodate refinements required by the search strategy.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: May 22, 2012
    Assignee: Xilinx, Inc.
    Inventors: Toader-Adrian Chirila-Rus, Wilson C. Chung
  • Pyloric valve devices and methods
    Patent number: 8182442
    Abstract: A pyloric valve is provided for inhibiting the flow of chyme through the pyloric region of the gastrointestinal tract. The pyloric valve includes a blocking portion having a plurality of disc-shaped flanges connected in series. The blocking portion may be disposed in a contracted position wherein the plurality of disc-shaped flanges is disposed in a stacked configuration and a resting position wherein the plurality of disc-shaped flanges is disposed in a linear configuration. The pyloric valve may further include a sleeve that may have a beveled distal end. The pyloric valve may be constructed of silicon. Also provided are methods of inserting and removing the pyloric valve, which each include a step of manipulating the support between its resting and contracted positions. Insertion and removal systems are also provided for use with the pyloric valve.
    Type: Grant
    Filed: April 9, 2009
    Date of Patent: May 22, 2012
    Assignee: ElectroCore LLC
    Inventors: Buket Grau, David Robert Gale, Sam Anne Musgrave, George McGee Perkins, Mark Jeffrey Edhouse, Marc Graham, Christopher Kadamus
  • Semiconductor device and method for operating the same
    Patent number: 8184496
    Abstract: A semiconductor device includes a sensing unit configured to sense whether a value of a programming sensing node is within a predefined range, a fuse connected to the programming sensing node, a programming voltage supplying unit configured to supply a programming voltage to the programming sensing node, and a transferring unit configured to transfer the value of the programming sensing node in response to the sensing result of the sensing unit.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: May 22, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jin-Youp Cha, Sang-Jin Byun
  • Positive-drive spiral conveyor
    Patent number: 8181771
    Abstract: A spiral conveyor for positively driving a conveyor belt along a helical path. The spiral conveyor includes a rotating cylindrical tower with parallel drive members extending from the bottom to the top of the tower on its periphery. Each drive member includes an outwardly protruding ridge that varies in height from the bottom to the top of the tower. The variations in height facilitate the belt's entry onto and exit from the tower and robust, positive driving engagement with the inside edge of the belt along the majority of its path along the tower.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: May 22, 2012
    Assignee: Laitram, L.L.C.
    Inventor: Casper Fedde Talsma
  • Sleep optimization based on system information block scheduling
    Patent number: 8185726
    Abstract: Methods and apparatuses are presented for sleep optimization based on system information block SIB scheduling. A method for invoking sleep states within user equipment (UE) is presented. The method includes decoding a broadcast control channel with a cell, determining a System Information Block (SIB) schedule associated with the cell, determining a sleep time interval based upon the SIB schedule, and placing the UE in a sleep state using the sleep time intervals. An apparatus for invoking sleep states within UE is presented. The apparatus includes logic configured to decode a broadcast control channel with a cell, logic configured to determine a SIB schedule associated with the cell, logic configured to determine a sleep time interval based upon the SIB schedule, and logic configured to place the UE in a sleep state using the sleep time intervals.
    Type: Grant
    Filed: April 25, 2007
    Date of Patent: May 22, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Ali Taha, Chih-Ping Hsu, Shawn C. Morrison, Vivek Ramachandran
  • Semiconductor memory device and method for operating the same
    Patent number: 8184500
    Abstract: A semiconductor memory device includes a plurality of banks, a first bank selection driving control signal generation unit configured to generate a plurality of first bank selection driving control signals corresponding to the plurality of banks in response to an active command signal and an address signal, a second bank selection driving control signal generation unit configured to generate a plurality of second bank selection driving control signals corresponding to the plurality of banks in response to one of a read command signal and a write command signal and in response to the address signal, and an internal voltage driver configured to selectively drive a plurality of internal voltage terminals corresponding to the plurality of banks in response to the plurality of first bank selection driving control signals and the plurality of second bank selection driving control signals.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: May 22, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Choung-Ki Song
  • Preamble channel decoding
    Patent number: 8184607
    Abstract: Rather than attaching a preamble to a data traffic subpacket, a preamble channel is transmitted along with a traffic channel. In a system wherein the data traffic subpackets are variably sized, preambles can also be variably sized if a target station can decode variably sized preambles. A method and apparatus for decoding variably sized preamble subpackets are presented herein.
    Type: Grant
    Filed: June 1, 2007
    Date of Patent: May 22, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Joseph P. Odenwalder, Sandip Sarkar, Yongbin Wei
  • Absorbent article
    Patent number: 8178748
    Abstract: An absorbent article for wearing in an undergarment. The absorbent article can include a nonwoven. The nonwoven can have a nonwoven body facing surface. The nonwoven can have a main body portion and pair of spaced apart flaps associated with the main body portion. Part of the main body portion can have a hydrophilic zone that is more hydrophilic than a portion of the flaps. The absorbent article can have film having a film garment facing surface wherein at least part of the film garment facing surface faces the nonwoven body facing surface.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: May 15, 2012
    Assignee: The Procter & Gamble Company
    Inventors: John Lee Hammons, Robert Ya-lin Pan, Brent Taylor Ginn, Brian Francis Gray, Casandre Maffett Walsh
  • Packaging container with surface ornamentation
    Patent number: D660145
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: May 22, 2012
    Assignee: The Procter and Gamble Company
    Inventors: Thomas John Tekulve, Jennifer Frankovich Rippe, Molly A. Hablutzel, John Stephen Eadicicco