Abstract: The invention relates to an ultrasonic linear motor (1) comprising a plate-type ultrasonic oscillator (2) with two planar parallel main faces, two end faces and two lateral faces and a displaceable element (9) that engages with at least one guide rail (10) and has two friction parts, said element interacting with the ultrasonic oscillator to cause friction via the lateral faces of the friction parts. The lateral faces of the ultrasonic oscillator are planar and are inclined at the same angle in relation to a longitudinal plane of symmetry, in such a way that the intersection lines between the planes of the lateral faces and the longitudinal plane of symmetry run parallel to the main faces of the ultrasonic oscillator. The friction parts of the displaceable element are interconnected by springs.

Abstract: A semiconductor device includes a first transmission line and a second transmission line disposed at different layers; a contact fuse coupled with the first transmission line and the second transmission line; a power driver configured to apply an electric stress to the contact fuse; and a fuse state output unit configured to output a fuse state signal having a logic level corresponding to an electric connection state of the contact fuse.

Abstract: A delay circuit includes first and second selective delay stages each including a number of unit delay cells to delay signals applied thereto; and a delay control unit configured to control selectively applying an input signal to the first selective delay stage or the second selective delay stage in response to a code combination of first and second selection signals and produce an output signal.

Abstract: Methods, devices, computer readable media and apparatus are presented for providing configurable task management, such as data collection management, on a wireless device. Task management provides conditions and associated actions which may be dynamically configured and implemented in conjunction with any application executed on the wireless device.

Abstract: A method of bridging a plurality of buses within a bus bridge can include determining whether a queue of the bus bridge includes a transaction request directed to a restricted address range and, for each received transaction request, determining whether an address to which the transaction request is directed is within the restricted address range. Each transaction request received by the bus bridge can be selectively rejected according to whether the address to which the transaction request is directed is within the restricted address range and whether the queue includes a transaction request directed to the restricted address range.

Abstract: A one-transistor type DRAM including a floating body storage element connected between a bit line and a source line and controlled by a word line comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arranged in a column direction, a plurality of clamp bit lines and reference bit lines arranged in a column direction, a cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a clamp cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, a reference cell array including the floating body storage element and formed in a region where the source line, the word line and the bit line are crossed, and a sense amplifier and a write driving unit connected to the bit line and configured to receive a clamp voltage and a reference voltage.

Abstract: A self-synchronizing system that provides a master system component and a master clock source to provide a stable timing reference to the master system component. Timing information is then propagated throughout the system via encoded transmissions containing the timing information, or conversely, propagated by request via a training sequence. All system components other than the master system component do not require a separate clock input, since frequency coherency is maintained by internal time bases that have been calibrated to the frequency of the propagated timing information.

Abstract: A negative voltage generator of a semiconductor memory device includes: a flag signal generation unit for receiving a temperature information code from an On Die Thermal Sensor (ODTS) to output a plurality of flag signals containing temperature information of the semiconductor memory device; and a negative voltage detection unit for detecting a negative voltage to output a detection signal for determining whether to pump a negative voltage, wherein a detection level of the negative voltage is changed according to the flag signals.

Abstract: A semiconductor memory device includes a voltage detector configured to detect a level of an external power supply voltage and an internal voltage generator configured to generate an internal voltage in response to an active signal and drive an internal voltage terminal with a driving ability corresponding to an output signal of the voltage detector. A method for operating the semiconductor memory device includes detecting a level of an external power supply voltage, based on a first target level, to output a detection signal; and generating an internal voltage in response to an active signal, and driving an internal voltage terminal with a driving ability corresponding to the detection signal.

Abstract: A semiconductor integrated circuit includes first and second bump pads configured to output data, a probe test pad coupled to the first bump pad, and a pipe latch unit configured to selectively transfer data loaded on first and second data lines to one of the first and second bump pads in response to a pipe output dividing signal during a normal mode, and sequentially transfer the data loaded on the first and second data lines to the probe test pad in response to the pipe output dividing signal during a test mode.

Abstract: Disclosed herein are systems and methods for reducing power plant CO2 emissions. In one embodiment, a method for reducing emissions in a combustion stream, comprises: combusting a gaseous stream to produce an exhaust stream comprising carbon dioxide, and separating CO2 from the exhaust stream by passing CO2 through a membrane to produce a CO2 product stream and a CO2 lean exhaust stream.

Abstract: A camera includes a CPU. The CPU individually detects a ratio of an object which exceeds a threshold value in a moving amount to a center area of an object scene and a ratio of an object which exceeds the threshold value in the moving amount to a peripheral area of the object scene. If differences between the respective detected ratios are large, the CPU sets a photographing mode to a sports mode. When a shutter button is operated, the object scene is photographed in accordance with a set photographing mode.

Abstract: A data input circuit includes a first data input unit, a second data input unit, and a clock unit. The first data input unit is configured to receive external data at rising edges of a data strobe signal and output the external data as first internal data in response to an internal clock. The second data input unit is configured to receive the external data at falling edges of the data strobe signal and output the external data as second internal data in response to the internal clock. The clock unit is configured to generate the internal clock using an external clock signal.

Abstract: A method for fabricating a semiconductor device includes forming a hard mask pattern over a substrate, forming a protection layer by transforming a portion of a sidewall of the hard mask pattern, forming a trench by etching the substrate using the hard mask pattern and the protection layer as an etch barrier, forming an isolation layer by filling the trench with an insulation material, removing the hard mask pattern, and performing a cleaning process. By forming the protection layer, it is possible to prevent the isolation layer from being lost during the removing of the hard mask pattern and the cleaning process and thus prevent generation of a moat.

Abstract: A semiconductor device includes: a first reference voltage generator for generating a first reference voltage; a first band gap circuit for dividing a voltage at a second reference voltage output node to produce a first and a second band gap voltages having a property relative to temperature variations; a first comparator for receiving the first reference voltage as a bias input and comparing the first band gap voltage with the second band gap voltage; and a first driver for pull-up driving the second reference voltage output node in response to an output signal of the first comparator.

Abstract: Described is a novel family of cell surface serpentine transmembrane antigens. Two of the proteins in this family are exclusively or predominantly expressed in the prostate, as well as in prostate cancer, and thus members of this family have been termed “STEAP” (Six Transmembrane Epithelial Antigens of the Prostate). Four particular human STEAPs are described and characterized herein. The prototype member of the STEAP family, STEAP-1, appears to be a type IIIa membrane protein expressed predominantly in prostate cells in normal human tissues. Structurally, STEAP-1 is a 339 amino acid protein characterized by a molecular topology of six transmembrane domains and intracellular N- and C-termini, suggesting that it folds in a “serpentine” manner into three extracellular and two intracellular loops. STEAP-1 protein expression is maintained at high levels across various stages of prostate cancer. Moreover, STEAP-1 is highly over-expressed in certain other human cancers.

Abstract: A delay locked loop (DLL) circuit includes a clock input buffer that generates a reference clock signal by buffering an external clock signal and outputs the reference clock signal by correcting a duty cycle of the reference clock signal in response to a duty cycle control signal. The DLL circuit also includes a timing compensation unit configured that generates a compensation reference clock signal by compensating for a toggle timing of the reference clock signal that is changed during the duty cycle correction operation in response to a timing control signal. The DLL circuit further includes and a duty cycle control unit that generates the duty cycle control signal and the timing control signal by detecting the duty cycle of the reference clock signal.

Abstract: A method of programming nonvolatile memory devices. A program operation is performed by applying a dummy program pulse having a pulse width wider than a pulse width of a program start pulse. A program operation is performed by applying the program start pulse. It is then verified whether a program has been completed as a result of the program operation. A program operation is performed by applying a step-shaped dummy program pulse, which has a second pulse width and has been increased by a second step voltage. A program operation is performed by applying a program pulse having a first step voltage and a first pulse width. It is then verified whether a program has been completed as a result of the program operation.