Patents Represented by Attorney Teradyne Legal Dept.
  • Patent number: 6850637
    Abstract: An optical inspection system with an improved illumination system. The improved illumination system used to illustrate the invention has a base formed from a printed circuit board. Substrates for mounting lighting elements, which are exemplified by light emitting diodes, are formed also on printed circuit boards. These circuit boards have serrated edges and the diodes are mounted to the serrations. This configuration allows the light emitting elements to be focused on the focal point. Also in the exemplary illumination system, the light emitting elements have different beam widths so that variations in the illumination intensity as a function of elevation angle are reduced.
    Type: Grant
    Filed: June 28, 2000
    Date of Patent: February 1, 2005
    Assignee: Teradyne, Inc.
    Inventor: John B. Burnett
  • Patent number: 6831473
    Abstract: A calibration circuit for use in automatic test equipment is disclosed. The calibration circuit includes a calibration signal driver having an output and a closed-loop transmission line coupled to the output of the calibration signal driver. A plurality of comparators having respective reference inputs, test signal inputs, and calibration inputs are coupled to the closed-loop transmission line. The plurality of comparators are adapted to selectively receive calibration signals generated by the driver in parallel along the closed-loop transmission line.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: December 14, 2004
    Assignee: Teradyne, Inc.
    Inventor: Cosmin Iorga
  • Patent number: 6780059
    Abstract: In one embodiment of the invention, there is disclosed an electrical connector connectable to a printed circuit board, and having ground conductors and signal conductors in a plurality of rows. Each of the plurality of rows includes a plurality of ground conductors and signal conductors, with each signal conductor having at least one corresponding ground conductor. Each signal conductor has a contact tail that electrically connects to the printed circuit board, and each corresponding ground conductor has at least two contact tails that electrically connect to the printed circuit board. The contact tails of the signal conductors and the ground conductors are positioned relative to one another so that for each signal conductor contact tail, there are ground conductor contact tails adjacent either side of the signal conductor contact tail.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: August 24, 2004
    Assignee: Teradyne, Inc.
    Inventors: Jason J. Payne, Huilin Ren, Philip T. Stokoe
  • Patent number: 6776659
    Abstract: In one embodiment of the invention, there is disclosed an electrical connector attachable to a printed circuit board and including an insulative housing. A plurality of signal conductors are provided, with each signal conductor having a first contact end, a second contact end, and an intermediate portion therebetween that is disposed in the insulative housing. A plurality of corresponding shield strips are provided, with each shield strip having a first contact end, a second contact end, and an intermediate portion therbetween that is disposed in the insulative housing adjacent one of the plurality of singnal conductors. Each intermediate portion of the shield strip has a surface with a first edge and a second edge, at least one of the first edge or the second edge being bent such that when the plurality of signal conductors and the corresponding shield strips are disposed in the insulative housing, the bent edge of the intermediate portion is directed toward the corresponding signal conductor.
    Type: Grant
    Filed: June 26, 2003
    Date of Patent: August 17, 2004
    Assignee: Teradyne, Inc.
    Inventors: Philip T. Stokoe, Jason J. Payne, Huilin Ren
  • Patent number: 6776645
    Abstract: A latch and release system for a connector disposable within a mating receptacle is provided, where the connector includes a body having a latch portion and a movable release portion, with the movable release portion having a biasing member. The latch and release system also includes an engaging member attached to the mating receptacle, with the engaging member having an engaging portion to engage the latch portion of the connector body when the connector is disposed in the mating receptacle. An abutment portion of the mating receptacle abuts the movable release portion of the connector body when the connector is disposed in the mating receptacle to cause the biasing member of the movable release portion to be biased.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: August 17, 2004
    Assignee: Teradyne, Inc.
    Inventors: Richard F. Roth, Richard P. Saulnier
  • Patent number: 6771061
    Abstract: A tester that is well suited for operation at high speeds or with narrow pulses. The tester includes a state based pulse shaping circuit that combines edge signals into a pulsed output signal. The circuit combines groups of set and reset signals. The edge signals define the start and stop of pulses in the output signal even if the set and reset edge signals overlap or successive set signals overlap or successive reset signals overlap. This circuit allows for a low cost and low power CMOS implementation of an output signal formatter.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: August 3, 2004
    Assignee: Teradyne, Inc.
    Inventors: Ronald A. Sartschev, Jun Xu
  • Patent number: 6769814
    Abstract: Generally, a fiber optic connector having at least one wafer, wherein the wafer holds at least one optical fiber, is provided. The wafer includes a retractable shroud, a body to receive the retractable shroud, and at least one biasing member. The biasing member is capable of being biased when the wafer contacts a corresponding mating wafer to cause the shroud to retract. In one specific detailed perspective and embodiment of the invention, the wafer as stated further includes the retractable shroud having a door that preferably opens outwardly and at least one ferrule that holds the optical fiber, where the ferrule is provided with an alignment pin. The biasing member includes a first biasing member, a second biasing member and a third biasing member. The first biasing member is capable of being biased to cause the alignment pin of the ferrule to open the door of the retractable shroud. The second biasing member is capable of being biased to cause the retractable shroud to be received by the body.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: August 3, 2004
    Assignee: Teradyne, Inc.
    Inventors: Sepehr Kiani, Richard F. Roth
  • Patent number: 6765796
    Abstract: A cover attaches to a circuit board and has an inlet at one side for receiving forced air and plurality of openings on its top surface through which heat sinks mounted on the circuit board partially extend. Air is made to flow into the inlet and out the exhaust openings, thereby concentrating airflow in the vicinity of the circuit board's heat dissipative components.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: July 20, 2004
    Assignee: Teradyne, Inc.
    Inventors: Mark S. Hoffman, David C. Drahms
  • Patent number: 6764349
    Abstract: An electrical connector system suitable for use in a matrix assembly. The electrical connector assembly has two connectors, each assembled from wafers. Certain of the connectors include a combination of signal and power conductors while others have only signal conductors. In this way, the signal density is maximized.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: July 20, 2004
    Assignee: Teradyne, Inc.
    Inventors: Daniel B Provencher, Thomas S. Cohen, Philip T. Stokoe
  • Patent number: 6760471
    Abstract: A system and method for compensating pixel values in an inspection machine for inspecting printed circuit boards includes an image acquisition system for providing pixel values from a digitized image to a compensation circuit. The compensation circuit applies one or more compensation values to the digitized pixel values to provide compensated digitized pixel values for storage in a memory. The compensated digitized pixel values are then available for use by an image processor which implements inspection techniques during a printed circuit board manufacturing process. With this technique, the system corrects the errors on a pixel by pixel basis as the pixel values representing an image of a printed circuit board are transferred from the image acquisition system to the memory.
    Type: Grant
    Filed: June 23, 2000
    Date of Patent: July 6, 2004
    Assignee: Teradyne, Inc.
    Inventor: Douglas W. Raymond
  • Patent number: 6741676
    Abstract: A method determines a structure of a subscriber line. The method includes searching a reference set for a match between the subscriber line and a model line of the reference set and identifying that the subscriber line has a specific physical structure. The match is based on electrical properties of the lines. The act of identifying is responsive to finding a match with one of the model lines that has the specific physical structure.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: May 25, 2004
    Assignee: Teradyne, Inc.
    Inventors: Ilia L. Rudinsky, Kurt E. Schmidt
  • Patent number: 6739918
    Abstract: An electrical connector assembly suitable for use in a matrix assembly. The electrical connector assembly has two connectors, each assembled from wafers. The individual wafers are shielded and separate shield pieces are positioned in one connector transverse to the wafers in that connector. Additionally, wafers in at least one of the connectors includes a compliant portion that allows the two connectors to be self-aligning.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: May 25, 2004
    Assignee: Teradyne, Inc.
    Inventors: Thomas S. Cohen, Daniel B Provencher, Philip T. Stokoe
  • Patent number: 6736546
    Abstract: A ferrule assembly, in a preferred embodiment, having a first ferrule, a second ferrule, and at least two alignment members to align the first and second ferrules during mating is provided. The first ferrule, the second ferrule and the alignment members interact at the mating interface of the first and second ferrules to provide three constraint lines. In one embodiment, the first ferrule has a body with at least one channel for receiving at least one optical fiber. The first ferrule body includes a first surface portion for retaining a first alignment member and a second surface portion for retaining a second alignment member, the first and second surface portions being V-shaped. The second ferrule has a body with at least one channel for receiving at least one optical fiber.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: May 18, 2004
    Assignee: Teradyne, Inc.
    Inventors: Sepehr Kiani, Ryan R. Vallance
  • Patent number: 6734688
    Abstract: Automatic test equipment adapted for testing a plurality of devices-under-test (DUTs) is disclosed. The automatic test equipment includes a mainframe computer and a test head coupled to the mainframe computer. The test head includes a low-profile tester interface having a first interface board and a device board. The device board engages contact points on the DUTs and includes a topside. A hard stop is mounted to the first interface board and defines a reference plane. The hard stop is adapted to engage the device board topside to vertically fix the device board, positionally with respect to the first interface board. The automatic test equipment further includes a compliant interconnect array adapted for compression between the first interface board and the device board.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: May 11, 2004
    Assignee: Teradyne, Inc.
    Inventors: Derek Castellano, Keith Breinlinger, Kevin P. Manning
  • Patent number: 6725115
    Abstract: Method and apparatus for providing dynamic testing of electronic assemblies during their manufacture. A production line includes a communication network to interconnect assembly and inspection equipment. Events impacting the manufacture of the assemblies are communicated among the equipment, allowing the testing to be dynamically adjusted in response to events. Dynamic adjustment allows the process to quickly detect defects introduced by events. The concept is illustrated with a production line that has a pick and place machine and an inspection station. When an operator changes a reel of components at the pick and place machine, the inspection station will switch test programs to quickly verify that the correct reel has been loaded.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: April 20, 2004
    Assignee: Teradyne, Inc.
    Inventors: Douglas W. Raymond, Nelson R. Saldana, John F. Wood
  • Patent number: 6722215
    Abstract: A compliance assembly is disclosed for use in a semiconductor tester testhead stand. The compliance assembly includes an airspring having compliance along a plurality of axes and a containment vessel adapted for receiving the airspring. The containment vessel includes walls that, when the airspring is loaded, control the compliance along the plurality of axes.
    Type: Grant
    Filed: June 18, 2002
    Date of Patent: April 20, 2004
    Inventors: Michael Caradonna, Sarosh Patel
  • Patent number: 6717115
    Abstract: A strip, leadframe or panel type handling device for use in testing semiconductor components. The handling device has a thermal plate assembly with embedded electrical resistance heaters. The heaters are separately controlled in zones to provide uniform temperature across the plate for elevated temperature testing. Cooling channels are formed in the plate. Intermingling channels are provided to allow different types of cooling fluids to be used to cool at different rates or hold a cold temperature at different levels. The cooling channels can likewise be provided in zones to promote temperature uniformity. Vacuum channels are used to hold the semiconductor parts under test in close contact with the thermal plate.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: April 6, 2004
    Assignee: Teradyne, Inc.
    Inventors: Andreas C. Pfahnl, John D. Moore
  • Patent number: 6709294
    Abstract: An electrical connector having electrical conductors in a plurality of rows is provided, wherein each of the plurality of rows includes a housing and a plurality of electrical conductors. Each electrical conductor has a first contact end connectable to a printed circuit board, a second contact end and an intermediate portion therebetween that is disposed within the housing. The housing includes a first region surrounding each of the plurality of electrical conductors, the first region made of insulative material and extending substantially along the length of the intermediate portion of the electrical conductors. The housing also includes a second region adjacent the first region and extending substantially along the length of the intermediate portion of the electrical conductors. The second region is made of a material with a binder containing conductive fillers.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: March 23, 2004
    Assignee: Teradyne, Inc.
    Inventors: Thomas S. Cohen, Robert A. Richard
  • Patent number: 6654914
    Abstract: Techniques are provided for improved fault isolation and fault reduction. A system for use with a data network includes multiple diagnostic units each adapted to communicate with the network including to a network user. A central controller is operatively connected to the diagnostic units, the controller being adapted to communicate with and coordinate operations of the diagnostic units, to instruct the diagnostic units to perform tests adapted to help isolate a network fault, and to analyze test results received from a diagnostic unit to attempt to determine the network fault. Various methods for improving fault isolation and fault reduction are also provided.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: November 25, 2003
    Assignee: Teradyne, Inc.
    Inventors: David M. Kaffine, Joseph S. Rosen, Peter H. Schmidt
  • Patent number: 6602095
    Abstract: A high speed, high density electrical connector. The connector is assembled from wafers. Each wafer is formed by molding a first dielectric housing over a shield plate. Signal contacts are inserted into the first dielectric housing and a second housing is overmolded on the first housing. Features are employed to lock the first and second housings together with the shield plate to provide a mechanically robust subassembly. The connector as formed has a good electrical properties, including precise impedance control and low cross talk.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: August 5, 2003
    Assignee: Teradyne, Inc.
    Inventors: Allan L Astbury, Jr., Thomas S. Cohen