Abstract: Disclosed are, inter alia, methods, apparatus, computer-readable media, mechanisms, and means for deterministically determining MPLS labels as functions of addresses of Forwarding Equivalence Classes (FECs), and using these determined labels in the forwarding of packets. By each packet switching device in a network deterministically determining the same MPLS label to use for each FEC, each packet switching device knows what label will be used by the other packet switching devices, without running Label Distribution Protocol (LDP) or another label publishing protocol. Additionally, this knowledge extends to all packet switching devices in a network, not merely neighboring packet switching devices, which allows a packet switching device to specify a stack of labels to define a desired path through the network for explicit path routing and/or fast rerouting of traffic without having to previously establish a tunnel or path using Resource Reservation Protocol (RSVP), for example.

Abstract: Disclosed is a hierarchy of individual schedulers with multiple scheduling lanes for scheduling items, such as, but not limited to packets or indications thereof, such that different classes of priority items can be propagated through the hierarchy of schedulers accordingly. A pipeline scheduler typically includes a root scheduler and one or more layers of schedulers with each of these layers including at least one scheduler. Each scheduler is configured to maintain items of different scheduling categories received from each of the particular scheduler's immediate children schedulers within the pipeline scheduler if any and from each immediate external source coupled to the particular scheduler if any, and to schedule the sending of the items of the different scheduling categories currently maintained to its parent schedule or external scheduler client. The items may correspond to packets, indications of packets, or any other entity.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable medium, mechanisms, and means for withdrawing routes based on a tag. One implementation receives one or more messages identifying multiple routes and a tag associated with the multiple routes. A routing database is updated to include the routes. A particular message associated with a route withdraw operation is received, with the particular message including an indication of the tag. The multiple routes are removed from the routing database in response to receiving the tag. For example, the tag may be a Border Gateway Protocol attribute, a Border Gateway Protocol communities attribute, or some other indication. When some devices do not support this feature, before other nodes will typically send to a particular device a message to withdraw multiple routes based on a tag, the particular device must first advertise that it has this capability and/or it will withdraw multiple routes based on a tag.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for filling token buckets of schedule entries, such as those used in, but not limited to, a scheduling system used in a computer or communications system (e.g., for sending packets, allocating processing resources, etc.). A scheduling system includes multiple schedule entries with a number of tokens and a last filled slot value. A period of time allocated for periodically updating the number of tokens for all of the schedule entries is divided into the slots, and each schedule entry is associated with a particular fill slot. Each particular schedule entry is repeatedly sequence through and updated during is corresponding slot; while in parallel, a next schedule entry to service is repeatedly identified and updated, while in parallel, ineligible entries schedule to be woken up for the current time slot are made eligible.

Abstract: A clock signal within an application-specific integrated circuit (ASIC) is characterized while operating a subsystem. Subsequently, also on the ASIC, a testing clock signal is generated, based on the characterization of the operative clock signal, for purposes of testing the subsystem operating according to the testing clock signal instead of the clock signal. The ASIC includes a clock signal characterization circuit configured to characterize a clock signal within the ASIC; a programmable testing clock signal generator configured for being programmed based on said characterization of the clock signal, and for generating a test clock signal based on its said programming; and the subsystem tested when operating according to the testing clock signal instead of the clock signal.

Abstract: Entries are arranged in hash tables with storage for multiple entries per bucket with entries being shifted among hash tables to make room for entries being added. A path is determined through a search of the hash tables to identify where to move entries during insert operations among the hash tables to make room for a data item being added. Entries are moved and a data item added according to the identified path. Many different types of searches may be used, such as breadth-first, depth-first, random walk, etc. Also, a free position at the end of the path may be identified by being a bucket having a lowest occupancy level in a first predetermined number of levels of the search, a first bucket encountered having space available or an occupancy level less than a predetermined threshold level, with the predetermined threshold level typically being less than that of a full bucket, etc.

Abstract: Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with subsets of the Forward Information Base (FIB) distributed among line cards in a switching device; especially wherein one or more of the line cards does not contain the complete FIB, and this line card forwards packets, for which it does not have the forwarding information, to another line card which has the forwarding information for the packet.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for applying features to packets in an order specified by a selected feature order template. By providing multiple feature order templates, a network device manufacturer can provide the user of the network device the ability to select among a variety of orders in which features are applied, while limiting the possible selectable orderings such as to those capable by the hardware and software of the network device, and/or to a subset of orderings thereof which has been thoroughly tested. Some devices further allow a user to define new feature order templates via a user interface.

Abstract: Intelligent allocation of programmable comparison operations may reduce the number of associative memory entries required for programming an associative memory (e.g., ternary content-addressable memory) with multiple matching definitions (e.g., access control list entries, routing information, etc.), which may be particularly useful in identifying packet processing operations to be performed on packets in a packet switching device. The higher-cost comparison operations, in terms of the number of associative memory entries required to natively support such operations, are allocated to one or more comparison evaluators (e.g., programmable logic and/or processing elements configured to evaluate one or more comparison operations) configured to evaluate an input value with one or more of the programmable comparison operations in order to generate and provide one or more values representing results of the evaluations to one or more associative memories for use in identifying the packet processing operations.

Abstract: An Ethernet Connectivity Fault Management (CFM) Area Boundary Translator is configured to translate incompatible CFM messages being sent between networks operating according to different CFM versions which are not fully compatible. Such translation may include the Ethernet CFM area boundary translator acts as a proxy in forwarding translated the CFM messages.

Abstract: Mechanisms for programming and performing combined interface and non-interface specific associative memory lookup operations for processing of packets are disclosed. One system includes multiple interfaces, a content-addressable memory, multiple memory entries and a lookup mechanism. The content-addressable memory includes multiple interface independent entries, multiple first interface dependent entries corresponding to the first interface, and multiple second interface dependent entries corresponding to the second interface. The lookup mechanism is configured to initiate lookup operations in order to produce the interface independent and interface dependent results.

Abstract: A hierarchical tree of deterministic finite automata (DFA) is traversed and/or generated based on a set of regular expressions. The hierarchical DFA includes a root DFA linked together with a set of leaf DFAs, and possibly a set of branch DFAs. The root DFA is always active and is responsive to an input string, as are any currently active branch and leaf DFAs. When a final state or arc is reached or traversed in any active DFA, a regular expression has been matched. The branch and leaf DFAs are activated in response to the root DFA or a branch DFA reaching or traversing an activation state or arc corresponding to the branch or leaf DFA. Active branch and leaf DFAs will become inactive when a termination state or arc is reached or traversed within the branch or leaf DFA. State explosion in the hierarchical DFA can typically be avoided by selectively grouping similar portions of the regular expressions together in branch and leaf DFAs.

Abstract: Different mechanisms are disclosed for translating native Media Access Control (MAC) addresses to and from corresponding hierarchical MAC addresses, and the use of such MAC addresses. A packet switch typically maintains a data structure relating native MAC addresses of certain devices with external MAC addresses, wherein each of the external MAC addresses is typically hierarchical in nature with a portion of the translated address identifying a switch local to the destination device and through which the destination device is to be reached. Other network elements can then readily determine where to route a packet with a destination identified by such a hierarchical MAC address without having to maintain such a large or complete database of MAC addresses as the packet can be routed to the switch based on a portion of the hierarchical address (e.g., typically without regard to the portion of the address identifying the actual destination device).

Abstract: Methods and apparatus are disclosed for using gap packets to create a bandwidth buffer over which packets can be sent to reduce or eliminate overflow conditions. One implementation sends a series of packets from a first device to a second device, the series of packets including interspersed information packets and gap packets. The first device determines when to insert the gap packets into the series of packets, and the gap packets received by the second device are dropped. The determination of when to insert one of the gap packets into the series of packets may be based on an occupancy level of a buffer, such as, but not limited to comparing it to a predetermined or variable threshold value. Also, the rate of sending gap packets and/or the size of the gap packets may be varied to adjust the size of bandwidth buffer created by the gap packets.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for policy-based processing of packets, including mechanisms for managing the policies. A user is authenticated and its user group identifier is identified. A packet is received and is associated with the user group identifier, and one or more fields (typically other than the source address field) of the packet are used to identify a second group identifier. A lookup operation is then performed on a policy based on the first and second group identifiers to identify a packet processing action to be performed on the packet. These identifiers are typically not network addresses, which disassociates the policy from physical network addresses (which often are dynamically assigned and may also vary based on the access point into the network of a user), and allows a switching device to process packets based on a policy stated using group identifiers.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for identifying matches to a series of regular expressions, with the series of regular expressions including a first regular expression followed by a second regular expression, which avoids the potential overlap of characters used in matching the first and second regular expressions, while allowing individual deterministic finite automata (DFAs) to be used, whether standalone or as a merged DFA, which decreases the number of states required to represent the series of regular expressions. This potential overlap of characters can be avoided by adding marking states in a merged DFA as “divergent” in order to mask (e.g., ignore) a matching of the second regular expression for the potential overlap, or by using another DFA corresponding to the second regular expression for use during this divergent period.

Abstract: Methods, apparatus, and other mechanisms are disclosed for generating accounting or other data based on that indicated in access control lists or other specifications, and typically using associative memory entries in one or more associative memory banks and/or memory devices. One implementation identifies an access control list including multiple access control list entries, with a subset of these access control list entries identifying accounting requests. Accounting mechanisms are associated with each of said access control list entries in the subset of access control list entries identifying accounting requests. An item is identified, and a corresponding accounting mechanism is updated. In one implementation, the item includes at least one autonomous system number. In one implementation, at least one of the accounting mechanisms is associated with at least two different access control list entries in the subset of access control list entries identifying accounting requests.

Abstract: A network-based call interface device is used for real-time packet protocol calls, such as, but not limited to, interfacing real-time calls between client devices and call services/destination devices. The network-based call interface device includes a virtual phone and a virtual server-phone communicating with each other. The virtual phone communicates with the call server making the network-based call interface device appear to the call server as a client device; and the virtual server-phone communicates with the client device making the network-based call interface device appear to the client device as call server.

Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for establishing a call across a network. For example, the network may include a first edge switch, a second edge switch, and an ATM core network coupled to the first and the second edge switches and configured to allow the second edge switch to communicate with the first edge switch. The second edge switch, being responsive to a received Q.2630.1 AAL2 message, is configured to send a first Private Network-Network Interface (PNNI) setup message to the first edge switch as part of establishing a call between or through one or more of the first and the second edge switches.

Abstract: Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets, especially for maintaining requisite packet orderings when distributing packets to be processed to different packet processing engines, may be particularly useful. For example, in response to a particular packet processing engine completing processing of a particular packet, a gather instruction is attached to the particular identifier of a particular ordered lock associated with the particular packet. If no longer needed for further processing, the packet processing engine is immediately released to be able to process another packet or perform another function. The gather instruction is typically performed in response to the particular ordered lock being acquired by the particular identifier, with the gather instruction causing the processed particular packet to be sent.