Abstract: Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets may be particularly useful. One implementation uses a locking request, acceptance, and release protocol. One implementation associates instructions with locking requests such that when a lock is acquired, the locking mechanism executes or causes to be executed the associated instructions as an acceptance request of the lock is implied by the association of instructions (or may be explicitly requested). In some applications, the ordering of the entire sequence of packets is not required to be preserved, but rather only among certain sub-sequences of the entire sequence of items, which can be accomplished by converting an initial root ordered lock (maintaining the sequence of the entire stream of items) to various other locks (each maintaining a sequence of different sub-streams of items).
Type:
Grant
Filed:
November 12, 2003
Date of Patent:
December 1, 2009
Assignee:
Cisco Technology, Inc.
Inventors:
John J. Williams, Jr., John Andrew Fingerhut, Kenneth Harvey Potter, Jr.
Abstract: Systems and methods are disclosed for implementing and using data structures comprised of a hierarchy of queues or linked list data structures. A queue or linked list typically comprises a distributor, a plurality of sub-queues or sub-linked lists, and a receiver. The distributor distributes a plurality of items to be added to the queue or linked list to the plurality of sub-queues or sub-linked lists in an order, and the receiver receives the items from these elements in the same order. Entries for the queues and/or linked lists may be stored in a common memory. Stages of selectors may be used to select a current queue or linked list and a particular sub-queue or linked list. The number of queues/linked lists and sub-queues/sub-linked lists is unbounded and can be sized according to the needs of the system, such as to overcome a memory access speed limitation.
Abstract: Data is protected using locks, with the protected data sometimes being included in the locking messages, which may reduce overall processing latency, and/or reduce a bandwidth requirement for and/or number of storage operations accessing the native storage of the protected data. For example, the lock manager receives lock requests from each of the requesters, and selectively grants the lock requests. The protected data is typically communicated in the locking messages when the lock is highly contested, or at least two request for access to the data are pending. The lock manager initiates the sequence by indicating in a grant message to a requester to include the protected data in its release message. The lock manager then copies this data received in the release message to its grant message to the next requestor.
Type:
Grant
Filed:
March 27, 2004
Date of Patent:
December 1, 2009
Assignee:
Cisco Technology, Inc.
Inventors:
John J. Williams, Jr., John Andrew Fingerhut, Jonathan Rosen
Abstract: Methods and apparatus are disclosed using a random indication to map items to paths and to recirculate or delay the sending of a particular item when a destination over its mapped path is unreachable, including, but not limited to the context of sending of packets across multiple paths in a packet switching system. In one implementation, a set of items is buffered, with the set of items including a first and second sets of items. The items in the first set of items are forwarded over a set of paths in a first configuration. The set of paths is reconfigured into a second configuration, and the items in the second set of items are forwarded over the set of paths in the second configuration. In one implementation, a recirculation buffer is used to hold items not immediately sent. In one implementation, the paths are reconfigured in a random fashion.
Type:
Grant
Filed:
January 15, 2002
Date of Patent:
November 3, 2009
Assignee:
Cisco Technology, Inc.
Inventors:
John J. Williams, Jr., Thomas Dejanovic
Abstract: Methods and apparatus are disclosed for storing tree data structures among and within multiple memory channels, which may be of particular use with, but not limited to tree bitmap data structures. A subtree (or entire tree) typically includes one or more leaf arrays and multiple tree arrays. One or more leaf arrays are typically stored in a first set of memory channels of N+1 sets of memory channels, the N+1 sets of memory channels including N sets of memory channels plus the first set of memory channels. Each of N contiguous levels of the multiple tree arrays are stored in a different one of said N sets of memory channels, wherein each of the multiple tree arrays at a same level of said N contiguous levels is stored in the same memory channel set of said N sets of memory channels. A memory channel for storing a particular level is typically assigned based on one or more current occupancy levels of the memory channels.
Type:
Grant
Filed:
March 31, 2008
Date of Patent:
November 3, 2009
Assignee:
Cisco Technology, Inc.
Inventors:
Vijay Rangarajan, Shyamsundar N. Maniyar, William N. Eatherton
Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for matching items with resources, such as, but not limited to packet processing contexts, output links, memory, storage, specialized hardware or software, compute cycles, or any other entity. One implementation includes means for maintaining distribution groups of items, means for maintaining differently aged resources queues, and means for matching resources identified as being at the head of the plurality of differently aged resources queues and as being primarily and secondarily associated with said distribution groups based on a set of predetermined criteria.
Type:
Grant
Filed:
April 5, 2005
Date of Patent:
October 20, 2009
Assignee:
Cisco Technology, Inc.
Inventors:
Doron Shoham, Rami Zemach, Moshe Voloshin, Alon Ratinsky, Sarig Livne, John J. Williams, Jr.
Abstract: Methods and apparatus are disclosed herein for classifying packets using ternary and binary content-addressable memory stages to classify packets. One such system uses a stage of one or more TCAMS followed by a second stage one or more CAMS (or alternatively some other binary associative memories such as hash tables or TRIEs) to classify a packet. One exemplary system includes TCAMs for handling input and output classification and a forwarding CAM to classify packets for Internet Protocol (IP) forwarding decisions on a flow label. This input and output classification may include, but is not limited to routing, access control lists (ACLs), quality of service (QoS), network address translation (NAT), encryption, etc. These IP forwarding decisions may include, but are not limited to IP source and destination addresses, protocol type, flags and layer 4 source and destination ports, a virtual local area network (VLAN) id and/or other fields.
Abstract: Routes are withdrawn based on a query defined in a withdraw message. One or more route update messages identifying multiple routes with associated attributes and Type-Length-Values (TLVs) are received, and a routing database is updated to include the routes and their associated attributes and TLVs. A particular message associated with a route withdraw operation is received, with the particular message including an indication of at least two specified values and an operator, with each of the specified values being an attribute or a TLV. One or more routes are withdrawn from the routing database matching a query defined based on the specified values and the operator. In one embodiment, each of said attributes is a Border Gateway Protocol attribute. One embodiment includes sending a message including an advertisement of supporting MP_AGGREGATE_WITHDRAW capability.
Type:
Grant
Filed:
March 11, 2005
Date of Patent:
October 6, 2009
Assignee:
Cisco Technology, Inc.
Inventors:
Keyur Patel, Chandrashekhar Appanna, Robert Raszuk
Abstract: Token buckets are used in a computer or communications system for controlling rates at which corresponding items are processed. The number of tokens in a token bucket identifies the amount of processing that is available for the corresponding item. Instead of storing the value of a token bucket as a single value in a single memory location as traditionally done, the value of a token bucket is stored across multiple storage locations, such as in on-chip storage and in off-chip storage (e.g., in a memory device). An indication (e.g., one or more bits) can also be stored on chip to identify whether or not the off-chip stored value is zero and/or of at least of a certain magnitude such that it may be readily determined whether there are sufficient tokens to process an item without accessing the off-chip storage.
Type:
Grant
Filed:
November 11, 2005
Date of Patent:
October 6, 2009
Inventors:
James Fraser Testa, Eyal Oren, Earl T. Cohen
Abstract: Eligible entries are scheduled using an approximated finish delay identified for an entry based on an associated speed group. One implementation maintains schedule entries, each respectively associated with a start time and a speed group. Each speed group is associated with an approximated finish delay. An approximated earliest finishing entry from the eligible schedule entries is determined that has an earliest approximated finish time, with the approximated finish time of an entry being determined based on the entry's start time and the approximated finish delay of the associated speed group. The scheduled action corresponding to the approximated earliest finishing entry is then typically performed. The action performed may, for example, correspond to the forwarding of one or more packets, an amount of processing associated with a process or thread, or any activity associated with an item.
Type:
Grant
Filed:
December 23, 2004
Date of Patent:
October 6, 2009
Assignee:
Cisco Technology, Inc.
Inventors:
Doron Shoham, Christopher J. Kappler, Anna Charny, Earl T. Cohen, Robert Olsen
Abstract: Methods and apparatus are disclosed for scheduling entities in a system, such as, but not limited to a computer or communications system. Typically, calendar scheduling is used as a primary scheduling mechanism, with spare time allocated to a secondary scheduling mechanism. The secondary scheduling mechanism can use a round robin technique or variant thereof, or any other scheduling methodology. A calendar entry is examined to determine whether to process a calendar scheduled entity corresponding to the calendar entry or to process a secondary scheduled entity. Which scheduling entity to process is typically determined based on an eligibility of an entity corresponding to the primary scheduled event, a scheduling mechanism indicator, and/or an entity indicator. These combinations of scheduling mechanisms can be used to identify which packets to send, queues or ports to access, processes or threads to execute, or for any other purpose.
Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, and mechanisms, for identifying admission control policies and enforcement of these admission control policies on packets destined for a route processor. A typical routing device includes: a route processor, a forwarding lookup mechanism for identifying packets destined for the route processor; a lookup mechanism for identifying admission control parameters for packets destined for the route processor; and an admission control enforcement mechanism for enforcing the identified admission control policy parameters for the packets.
Type:
Grant
Filed:
July 12, 2005
Date of Patent:
August 25, 2009
Assignee:
Cisco Technology, Inc
Inventors:
John H. W. Bettink, David Delano Ward, Jianyu Chen, Paul Mattes, Norbert Brotz
Abstract: Memory is shared among multiple information channels, which may be of particular use for storing streams of packets. Memory allocation information is maintained which can be used to identify the current number of memory segments (e.g., some definable amount of memory) allocated for each of the multiple channels as well as the available number of shared memory segments. Items, such as, but not limited to data, packets, etc., are received and stored in the memory according to the memory allocation information. After a first processing stage for an item, the memory allocation information is updated to reflect an expected number of available memory segments to become available for the respective channel after a subsequent second processing stage. After the second processing stage is completed for an item, its number of memory segments are de-allocated based on the expected available data. In one embodiment, these memory segments are de-allocated one at a time.
Type:
Grant
Filed:
January 22, 2005
Date of Patent:
July 21, 2009
Assignee:
Cisco Technology, Inc.
Inventors:
Doron Shoham, Rami Zemach, John J. Williams, Jr.
Abstract: A virtual address storage system, which may be of particular used in generating fragmented packets, is implemented using a linked list of data segments. Multiple storage segments linked together in a linked list data structure are maintained to represent a virtual contiguous block of storage to be accessed based on a virtual address. Virtual address to corresponding data segment pointer associations are maintained for identifying a data segment corresponding to a particular address within the address space. In response to an identified address in the address space, a particular closest dynamic recently used association is identified and used to traverse to the desired data segment (e.g. rather than traversing from the beginning of the linked list), and one of the dynamic recently used associations is updated. A packet can be stored in this address space along with newly generated packet headers and tails for the multiple fragmented packets.
Abstract: Disclosed are mechanisms for initiating and performing tasks by a gang of members. A member of a gang identifies an event or other condition which requires notification to and/or action to be taken by at least a subset, if not all the other members of the gang. The gang member notifies other gang members by sending a message, such as that using reliable group communication using multicast and/or unicast messages. The information notified to other gang members and/or actions to be performed are extensible to meet the needs of the wide-variety of possible applications. A small list of example subject areas of these applications includes collecting, distributing, updating, responding to, and/or other processing of error conditions, routing information (e.g., between systems, from a route processor to line cards within a system, etc.), configuration information, flow control information, statistics or other values, etc.
Type:
Grant
Filed:
November 25, 2003
Date of Patent:
July 14, 2009
Assignee:
Cisco Technology, Inc.
Inventors:
Stephen Paul Belair, David Delano Ward, Sudhakar Mamillapalli
Abstract: Methods and apparatus are disclosed for changing the bandwidth or other traffic characteristic of an established packet call in response to an identification of the requirements of the call. In response to the detection of a type of call, such as a fax or modem call, ATM signaling is performed with peer signaling agent(s) located in the ATM network to increase the bandwidth of an already established portion of a call through the ATM network. This signaling typically includes sending a call modify request message and receiving a modify acknowledgement message, with these messages typically, but not limited to, conforming with a Q.2963 signaling standard.
Abstract: Sets of ranges typically are maintained using an associative memory and may be used to identify a matching range based on a query point or query range and to maintain sorted elements for use, such as in providing priority queue operations. In one implementation, ranges are added to a set of ranges by determining a longest common prefix of a starting point and an ending point of the range, extending this longest common prefix by appending a bit to create a particular extended longest common prefix, and then storing it in the set of extended longest common prefixes. The set of extended longest common prefixes is then processed based on the query point or range to identify the matching range. Additionally, one implementation uses bands for identifying ranges, where the band is formed from the starting and ending points to the longest common matching prefix of the these points.
Abstract: Stored in the leaf nodes of a data structure that can be used for identifying the longest prefix matching an address are corresponding values from multiple forwarding information bases. A single common address lookup data structure (e.g., a tree, trie, etc.) can be used, and a leaf node can contain information from multiple forwarding information bases. If lookup operations are performed for a single address in multiple forwarding information bases, the single common address lookup data structure may only need to be traversed once. For example, the forwarding information for another forwarding information base may be stored in the same leaf, further down in the data structure requiring traversal from the current position, or above requiring traversal from the root of the lookup data structure. Information can be stored in the leaf node to indicate which traversal option is appropriate for a particular forwarding information base.
Type:
Grant
Filed:
October 21, 2005
Date of Patent:
June 23, 2009
Assignee:
Cisco Technology, Inc.
Inventors:
David Delano Ward, Pawan Uberoy, John H. W. Bettink, Shyamsundar N. Maniyar
Abstract: Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for providing a JTAG to system bus interface for accessing embedded analysis system(s). JTAG commands are received and converted into commands sent out a bus to a device including an embedded analysis instrument, with results received over the bus forwarded out the JTAG interface to an external device. Such a JTAG to system bus interface may eliminate the need to provide separate JTAG TAP interfaces on each ASIC of a board, and/or eliminate the need to daisy chain multiple TAP interfaces of multiple ASICs in order to provide a single TAP interface for accessing the multiple embedded testing instruments.
Type:
Grant
Filed:
July 26, 2006
Date of Patent:
June 2, 2009
Assignee:
Cisco Technology, Inc.
Inventors:
Hongshin Jun, Gyaneshwar S. Saharia, William Eklow
Abstract: Methods, apparatus, data structures, computer-readable media, and mechanisms may include or be used with a hierarchy of schedules with propagation of minimum guaranteed scheduling rates among scheduling layers in a hierarchical schedule. The minimum guaranteed scheduling rate for a parent schedule entry is typically based on the summation of the minimum guaranteed scheduling rates of its immediate child schedule entries. This propagation of minimum rate scheduling guarantees for a class of traffic can be dynamic (e.g., based on the active traffic for this class of traffic, active services for this class of traffic), or statically configured. One embodiment also includes multiple scheduling lanes for scheduling items, such as, but not limited to packets or indications thereof, such that different categories of traffic (e.g., propagated minimum guaranteed scheduling rate, non-propagated minimum guaranteed scheduling rate, high priority, excess rate, etc.
Type:
Grant
Filed:
December 23, 2004
Date of Patent:
April 21, 2009
Assignee:
Cisco Technology, Inc
Inventors:
Earl T. Cohen, Robert Olsen, Christopher J. Kappler, Anna Charny