Abstract: A method for fracturing or mask data preparation or proximity effect correction is disclosed which comprises the steps of inputting patterns to be formed on a surface, a subset of the patterns being slightly different variations of each other and selecting a set of characters some of which are complex characters to be used to form the number of patterns, and reducing shot count or total write time by use of a character varying technique. A system for fracturing or mask data preparation or proximity effect correction is also disclosed.

Abstract: A method for manufacturing a surface, the surface having a multiplicity of slightly different patterns, is disclosed with the method comprising the steps of designing a stencil mask having a set of characters for forming the patterns on the surface and reducing shot count or total write time by use of a character varying technique. A system for manufacturing a surface is also disclosed.

Abstract: In some embodiments, a method of forming a photovoltaic cell includes (1) forming a cleave plane in a donor body so as to define a lamina to be bonded to a receiver element and exfoliated from the donor body; (2) prior to bonding, pre-heating the donor body without the receiver element to a temperature of greater than about 200° C. for a first time period that is less than a time period required for exfoliation of the lamina from the donor body; (3) cooling the donor body after pre-heating the donor body; (4) bonding the donor body to the receiver element; and (5) heating the bonded donor body and receiver element for a second time period so as to complete the exfoliation of the lamina from the donor body. Numerous other aspects are provided.

Abstract: A method is disclosed in which a plurality of variable shaped beam (VSB) shots is used to form a desired pattern on a surface. Shots within the plurality of shots are allowed to overlap each other. Dosages of the shots may also be allowed to vary. The union of the plurality of shots may deviate from the desired pattern. The plurality of shots may be determined such that a pattern on the surface calculated from the plurality of shots is within a predetermined tolerance of the desired pattern. In some embodiments, an optimization technique may be used to minimize shot count. In other embodiments, the plurality of shots may be optionally selected from one or more pre-computed VSB shots or groups of VSB shots. The method of the present disclosure may be used, for example, in the process of manufacturing an integrated circuit by optical lithography using a reticle, or in the process of manufacturing an integrated circuit using direct write.

Abstract: A method for manufacturing a surface, the surface having a multiplicity of slightly different patterns, is disclosed with the method comprising the steps of designing a stencil mask having a set of characters for forming the patterns on the surface and reducing shot count or total write time by use of a character varying technique. A system for manufacturing a surface is also disclosed.

Abstract: Various embodiments of the present invention relate to particle beam writing to fabricate an integrated circuit on a wafer. In various embodiments, cell projection (CP) cell library information is stored in the form of a data structure. Subsequently, the CP cell library information is referenced by a writing system. The patterns are written on the wafer depending on the referenced CP cell library.

Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

Abstract: A photovoltaic cell has electrodes, p- and n-junctions, and a heat sink. The heat sink is on a side of the cell opposite to the light-receiving side of the photovoltaic cell. The photovoltaic cell may also have heat-conducting channels within an interior of the photovoltaic cell that conduct heat from the interior of the photovoltaic cell to the heat sink. The heat sink can remove heat caused by light absorbed by the photovoltaic cell but not converted to electricity as well as heat generated by resistance to high current passing through electrodes of the photovoltaic cell. A module formed of such cells can exhibit greater energy conversion efficiency as a result of the ability to dissipate the heat. A method of making a solar cell or module involves e.g. laminating a heat sink to a photovoltaic cell as described above.

Abstract: The present invention relates to a launching device for a flying toy. The launching device facilitates the transition of the flying toy from a resting state to a flying state. The launching device may include elements for holding one or more parts of the flying toy in a retracted position while the flying toy is in a resting state and for releasing the parts when the flying toy launches into a flying state. According to the invention, the launching device includes a launch-assist mechanism that provides a force to facilitate the launch of the flying toy.

Abstract: The present invention is a toy launcher which is transfigurable from a compacted state to an operative state for launching projectiles. In one embodiment, the launcher utilizes a hand-pressurized air pump for providing the launching power, and may accommodate multiple types of projectiles to be loaded in the gun at the same time. Projectiles may include, for example, a bolo bullet, grapnel, or miniature missiles. Auxiliary retractable features such as targeting components and a flashlight with a logo projector may be added to enhance the play value of the invention.

Abstract: A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

Abstract: An analog-to-digital conversion circuit and a method for calibrating an analog-to-digital conversion circuit are provided. A digital translation of an analog voltage is analyzed to determine a characteristic value of the analog voltage. A reference voltage, with which the digital translation is generated, is set to a value that is a minimum amount greater than the characteristic value. Additional embodiments include setting an offset voltage, with which the digital translation is also generated.

Abstract: A method for particle beam lithography, such as electron beam (EB) lithography, includes predefining a stencil design having a plurality of cell patterns with information from a cell library, fabricating the stencil design, synthesizing a functional description into a logic circuit design after predefining the stencil design so that one or more characteristics of the stencil design are considered during synthesizing of the functional description into the logic circuit design, optimizing the logic circuit design, generating a layout design from the optimized logic circuit design, and forming the logic circuit on a substrate according to the stencil design and the layout design.

Abstract: A voltage regulator circuit and method are provided for regulating a voltage accurately in response to rapid variations in the regulator's load. The voltage regulator utilizes a hybrid loop; an embodiment of such utilization is exemplified by circuit 300. Amplifier 301 controls the current flowing through pass element 303 from an unregulated input voltage node Vin to a regulated voltage output node Vout. The regulated output voltage is provided to load 311 so that the voltage across the load stays constant regardless of variations in the current it pulls. The value of the regulated voltage is set by feedback network 302 and the input voltage at node Vref. The regulator feedback loop formed by amplifier 301, pass element 303, and feedback network 302 regulate the voltage at Vout in response to low frequency perturbations in load 311. In response to high frequency perturbations, a sensing network triggers control circuitry 310. Such a sensing network is exemplified in this embodiment by comparators 308 and 309.

Abstract: An amplifier circuit and method for amplifying a signal efficiently over a plurality of power ranges. The amplifier circuit including a strong amplifier which is efficient over a first power range and a weak amplifier which is efficient over a second power range. An impedance transformation circuit is used for generating a higher potential and providing increased efficiency when the second range of power is present. A circuit biases active the strong amplifier when the first power range of is present and biases active the weak amplifier when the second power range is present.

Abstract: A mount for a semiconductor device has a first surface with at least one contact region and a second surface. The mount has a substrate to receive the second surface of the semiconductor device and a planar element. The planar element has an aperture sized to surround the semiconductor. A first surface of the planar element is mounted to the substrate and is located to surround the semiconductor device such that the semiconductor device is aligned by the aperture. The mount further has means for mounting the semiconductor device to the substrate in an aligned position. Some embodiments include a method of making and/or using such a mount.

Abstract: A frequency synthesizer (50, 70) including an edge-detection circuit (51, 60) for disabling elements of the frequency synthesizer (50, 70) prior to start-up. The edge-detection circuit detects a transition edge of a reference-clock signal (ref_clk) of the frequency synthesizer (50, 70) and enables elements of the frequency synthesizer (50, 70) upon the detection of the transition edge.

Abstract: A system, including an alarm which is synchronized with a coffeemaker, is used to coordinate wake-up time with coffee brewing time. In one embodiment of the invention, the alarm includes an alarm timer, an alarm controller, alarm input (e.g., dial or button), a speaker, circuitry for sound generation and a display. A user sets the alarm timer, and the speaker is capable of providing a sound to wake the user at the set time. The circuitry for sound generation is capable of generating a tone and transmitting the tone with the same speaker. This tone is transmitted to an electric coffeemaker which includes, a tone receptor (e.g., microphone and amplifier), and coffee brewing circuitry. The tone receptor receives the tone generated by the alarm and forwards related data to the coffee brewing circuitry. The coffee brew cycle is activated in response. The alarm may be an alarm clock radio and the speaker may transmit an ultrasonic or audible tone.

Abstract: A startup circuit 200 and method 700 is provided for quickly starting up a resonator based oscillator. Tunable oscillator 201 provides an impetus signal to oscillator 205 through capacitor 202. The impetus signal has a frequency that is an estimate of the resonant frequency of resonator 205. The circuit measures the frequency of oscillator 204 and the frequency of tunable oscillator 201. The circuit then adjusts the frequency of tunable oscillator 201 such that the frequency of the tunable oscillator is substantially equal to the resonant frequency of the resonator 205 and stores a data state necessary for the tunable oscillator 201 to generate a signal with this target frequency in the future. During an ensuing startup cycle the stored data state causes the impetus signal delivered by tunable oscillator 202 to be substantially equal to the target frequency of oscillator 204 which improves startup performance.

Abstract: A calibration circuit (17) for calibrating a frequency synthesizer (10) having a voltage-controlled oscillator (VCO) (15) with a plurality of switched-capacitor arrays (CA1-CAn). The calibration circuit (17) counts a predetermined number of periods of the reference-clock signal (ref_clk) and divide-clock signal (div_clk) of the frequency synthesizer using a fast clock signal (fastclk). The fast-clock signal (fastclk) has a frequency greater than either the reference-clock signal (ref_clk) or the divide-clock signal (div_clk), enabling significantly faster calibration of the frequency synthesizer (10) than would be possible using the reference-clock signal (ref_clk). The calibration circuit (17) compares the count of the periods of the reference-clock signal (ref_clk) and the divide-clock signal (div_clk) and varies the tank signal of the VCO (VCO_tank_setting) until the count of the periods is substantially equal.