Abstract: An alternator/synchronous motor structure provides varying-reluctance paths for radially directed, unidirectional magnetic fields by means of a unique rotor-stator configuration in which inner- and outer-rotor poles and a rotor pole-connecting means surround one end and the inner- and outer-cylindrical surfaces of a hollow cylindrical stator. At least one of the inner or outer poles includes at least one field concentrator member. Optional excitation field may be provided by a stationary winding requiring no brushes for energizing or by permanent magnetization.

Abstract: A zero-power programmable bit circuit comprised of a programmable-inverter means with an isolation transistor and with an inverter-buffer. The programmable-inverter means is includes at least one enhancement-mode transistor pair with common floating gates and includes a diode-connected transistor. The isolation transistor protects the inverter-buffer from programming voltages. The inverter-buffer may be comprised of an inverter with a feedback transistor.

Abstract: An induction-motor structure having a synchronous-rotor and an induction-rotor in which inner- and outer-synchronous-rotor poles and a synchronous-rotor-pole connector surround the inner-cylindrical surface of the hollow cylindrical induction rotor, the outer-cylindrical surface of a hollow cylindrical stator core having alternating-current windings and surround the ends of that induction rotor and that core. At least one of the rotor poles includes magnetic field concentrators. A stationary field winding mounted on the end of the stator may be used adjust power factor.

Abstract: A fuse circuit for an integrated circuit chip which includes a non-volatile memory element, a circuit programmer for the memory element, and a read circuit for detecting the programmed states of the memory element and providing output signal levels corresponding to the programmed states. A switch is coupled to the read circuit output and switches from an open to a closed position in response to a selected output signal level.

Abstract: A circuit for applying reading, programming and erasing voltages to a wordline in a floating-gate-type EEPROM cell array comprising four P-channel transistors and two N-channel transistors as well as four switches. The circuit comprises a two-transistor inverter with a feedback transistor and three isolating transistors that prevent excessive currents and voltages from damaging internal and external circuit components.

Abstract: A single-ended sense amplifier for use in integrated-circuit logic arrays. The sense amplifier circuit uses five field-effect transistors in a unique configuration that uses positive feedback to increase the output speed of response while at the same time allowing layout in the narrow pitch of one bitline of an integrated-circuit logic array.

Abstract: A driver circuit for applying both read and program voltages to a wordline of an integrated-circuit memory-cell logic array. The driver circuit is comprised of a series driver transistor pair, of a driver enabling means for enabling and disenabling one of the transistors of the driver transistor pair, and of a latching means. The driver transistor used during read operation may be constructed with a relatively short source-drain channel, permitting faster access speed during read operation of the circuit.

Abstract: A reconfigurable circuit operating in a test mode and a normal operating mode includes a memory array (10) which has a row decoder (12) for addressing the memory elements therein. The row decoder (12) has a fused switch (18) for referencing the output circuits thereon to either a standard reference voltage or an external reference voltage. The memory array (10) has a fused switch (22) associated therewith for referencing the charging voltage for the memory cells to either the positive reference voltage in the circuit or to an external variable voltage. The fused switches (18) and (22) are operable to switch to internal references for the normal operating mode and to the external variable voltages for the test mode.

Abstract: A process for making a semiconductor integrated circuit which has electrodes, contacts and interconnects composed of a multilayer structure including a layer of polycrystalline silicon with an overlying layer of a refractory metal silicide such as MoSi.sub.2 or WSi.sub.2. Adhesion of the metal silicide to the polysilicon is enhanced by forming a thin silicon oxide coating on the polysilicon before sputtering the metal silicide. The resulting structure has low resistance but retains the advantages of polysilicon on silicon.

Abstract: A process is disclosed for making a conductive interconnecting path formed between two conductive areas of an integrated circuit, the conductive areas separated by at least an insulating layer of silicon nitride over a layer of oxide. The interconnecting path is formed by depositing a thick insulator coating, over the conductive and non-conductive areas then forming a vertical-walled trench, with said silicon nitride acting as an etch stop, in the thick insulator between conducting areas, then filling the trench with conductive material using chemical vapor deposition, and finally removing conductive material except for that conductive material deposited in the trench.

Abstract: An electrically programmable memory cell of a type having a source, a drain, a floating gate and a control gate formed over a face of a semiconductor substrate in which a ring region of material doped similarly to the substrate encloses the source, drain and gates and extends to a surface of the substrate around its length. Drain and source coupling regions of material doped oppositely to the substrate contact the drain and source, respectively, within the ring and extend under the ring to the substrate surface outside of the ring defining drain and source contact regions, respectively. A contact outside the ring to the control gate is provided by a gate coupling region also extending under the ring to a substrate surface on either side thereof. An interconnect couples the floating gate to the gate coupling region. A non-light transmitting, electrically conducting shield extends over the cell contacting the ring region around its periphery at the substrate surface.

Abstract: An electrically erasable programmable memory device which includes a floating gate, heavily doped source and drain regions in which one side thereof is laterally spaced from the floating gate, and the other side has a lightly doped "reach-through" region between the heavily doped region and the channel that underlies the floating gate. A control gate overlies the floating gate. The oxide thickness between the gate and channel is sufficiently thin such that electron tunnleing takes place between the floating gate and the "reach through" region.

Abstract: A memory array having two separate sets of parallel bit lines, and a word line intersecting the sets of bit lines. The memory cells are floating-gate MOS transistors having gates coupled to associated ones of the word lines and source-to-drain paths connected between alternating ones of the sets of bit lines and ground lines.

Abstract: A memory device is described which has the capability for testing portions of its circuitry with a variable test voltage, while allowing the remainder of the circuit to not be affected by variations in the test voltage. A specific example of a test utilizing this feature is a test directed to the leakage of stored charge in a dynamic memory cell through its access transistors controlled by the row lines. A circuit is disclosed which connects a test voltage terminal through a first fuse to the node to which the row decoder biases the unselected row lines. A second fuse and associated circuitry decouples the normal reference supply from this particular node, but does not affect the presence of the reference supply elsewhere in the memory device. The voltage of the test voltage terminal may be modulated to determine the voltage at which the access transistors in the array cause stored charge to leak during a memory cycle which selects another row in the array.

Abstract: An electrically programmable read only memory cell formed in a face of a semiconductor substrate which includes a floating gate transistor having a floating gate and a control gate formed at least partially in a trench in the substrate. The trench has bottom corners sufficiently sharp so as to enhance the likelihood of tunnelling between corner regions of the trench and the floating gate over that between planar surface regions of the trench and floating gate.

Abstract: An array of programmable memory cells having spaced apart bit lines, spaced conducting word lines crossing over the bit lines and electrically conductive lead lines crossing over the word line which includes electrically conductive contacts between lead lines and corresponding bit lines. Each contact is located at an opposite side of a selected number of word lines to contacts between adjacent lead lines and associated bit lines so that when viewed in plan the contacts are staggered from one lead line to the next.

Abstract: A sense amplifier for a read only memory cell array which includes a dynamic NOR circuit having high impedance inputs coupled to bitlines of the array. An inverter circuit has an input coupled to an output of the dynamic NOR circuit. An output buffer circuit has an input coupled to an output of the inverter circuit.

Abstract: A method for fabricating a static induction transistor starting with a high resistivity substrate on which a gate-source structure is formed. The gate-source structure is covered by a supporting layer and the wafer is etched to desired thickness. Ions are implanted in the etched surface and a drain electrode is deposited. A thick metal support layer and heat sink is electroplated on the drain electrode.

Abstract: A method for fabricating a gate-source structure for a recessed-gate static induction transistor. Source impurities are implanted prior to forming the recessed gates. The recessed gates are formed by a first isotropic etching step and a second anisotropic etching step which results in a unique overhanging protective layer used to protect the walls of the grooves during implantation of gate impurities in the bottom of the grooves. Implantations are driven and activated to form gate and source regions, the protective layer is removed and metal deposited to form electrodes. The procedure minimizes the required number of masking steps and associated mask registration problems.

Abstract: A high efficiency controlled direct current source for operating high pressure mercury or metal halide lamps for use as substitutes for ordinary incandescent lamps. The circuit includes a voltage sensitive circuit for pulsed starting of the arc discharge lamp as well as for the activation of an auxiliary incandescent filament during the warm-up or hot restart of the arc.