Abstract: A coaxial cable 24 has an outer conductor 74 surrounding an inner conductor 70. A portion 76 of the inner conductor 70 is stripped of insulation and extends beyond the end of the outer conductor at a cable end 30. A circuit board 12 has a major surface and defines an elongated slot 34. A connection end of the slot is defined by a stop portion of the board 36, and a conductive pad 60 is provided on the board surface adjacent the stop portion at the end of the slot. The stripped portion 76 of inner conductor 70 is connected to the conductive pad 60, and at least a portion of the outer conductor 74 is received in the slot, and may be connected to another contact on the board. The stop portion of the slot is defined as a peninsular connection tab 54 by an elongated hole 50 formed on each side of said stop portion 36 of said slot. The distance between the sides of the conductive pad 60 and the near edges of the elongated holes 50 is selected to provide a predetermined transition impedance.

Abstract: A stand for removably securing a housing of an electrical instrument to another structure. The stand has a support arm connected to the housing, with a free end movable with respect to the housing. A grip element is connected to the arm and is movable over a range of positions along the arm. The grip element has a resilient spring portion biased toward a neutral position near the arm, and the spring portion is movable to a flexed position away from the arm. Thus, the instrument may be secured to a structure by biasing the spring portion against a portion of the structure, often by capturing part of the structure between the spring and the housing, or between the spring and the arm.

Abstract: An elongated bail handle for an electronic instrument housing with opposed ends providing handle mounts. The handle has an elongated intermediate portion extending the width of the instrument, and a pair terminal arm portions each connected to the intermediate portion and having a free end for connection to a respective end surface of the housing. The intermediate portion defines an elongated bore, and a reinforcing bar laterally spans the bore to connect opposed walls of the intermediate portion. The arm and bore may have an oblong cross section, with the bar spanning the short span. The bar may define a passage, and an overmolded handle grip encompassing the reinforcing bar may have material filling the passage to secure it to the handle.

Abstract: A method of analyzing and displaying waveforms by acquiring an electrical signal, converting it into a stream of digital data points, and sequentially storing each data point to a memory device. Then, analyzing each of the data points to detect whether the data point is an anomalous data point outside of a preselected range. Until an anomalous data point is detected, the steps of acquiring, converting, storing, and analyzing data are repeated. Shortly after the anomalous data point is detected, storage of the data points to the memory device is stopped, so that the anomalous data point and adjacent data points are preserved in memory. Then, the anomalous data point is displayed, preferably along with the immediately preceding and succeeding data points.

Abstract: One or more recently acquired waveform data sets are maintained in memory after they are initially rasterized. During repeated waveform acquisitions, when the trigger and new waveform acquisition rates become so low that rasterizer time is being wasted, one or more of the most recent previously acquired waveforms are re-rasterized and displayed again to maintain the display until another newly acquired waveform becomes available. The rasterizer's readiness to re-rasterize a previously rasterized waveform data set can be qualified with a pre-determined or programmable time delay, thereby providing more flexibility for external circuitry and controllers to optimize utilization of the rasterizer's behavior. The method of this invention works especially well with rasterizers that produce some form of randomization in their outputs.

Abstract: To increase the percentage of time that an input signal is actively monitored, a digital oscilloscope has an acquisition system (100) that includes an analog-to-digital converter (15), an acquisition memory (40), an acquisition rasterizer (50), and a raster acquisition memory (60). The rasterizer contains circuitry (52) for concurrently rasterizing and combining the results of several acquisitions together and with a stored composite raster image to produce a new composite raster image, while additional acquisition records are being created and stored in the acquisition memory. A display system 200 takes the composite raster images after they contain the results of many acquisitions and overlays these single-bit raster images on a multi-bit raster image that is then decremented to produce a simulated persistence effect.

Abstract: A method and apparatus for measuring time intervals between electrical signals. A coincidence detection circuit is adapted to detect coincidence or near coincidence of two signals and to provide for selection from a plurality of predetermined delays to remove the coincidence. If the two input signals are periodic and have the same frequency, the apparatus also provides a signal from which both the time delay between the signals and the period of the signals may be determined at substantially the same point in time.

Abstract: A method and apparatus for digitally sampling electrical waveforms. A sampling circuit for sampling an electrical signal, a digitizing circuit for digitizing the samples produced by the sampling circuit and an acquisition memory for storing the samples are employed, the acquisition memory being partitioned into a plurality of frames. Each frame is triggered to store samples associated with a respective triggering event. After substantially all of the frames have been triggered, the contents of the acquisition memory are retrieved from the acquisition memory, filtered in an equalization filter and stored in a waveform memory for ultimate display as an ET record under software control. A plurality of digitizing circuits associated with respective inputs of a multi-channel digital sampling oscilloscope are interleaved to increase the sampling rate.

Abstract: A Videocassette Recorder including VPS (Video Program System) and VPT (VCR Programmed by Teletext) automatic programming capability continuously compares preprogrammed VPS data to incoming VPS time codes for the currently running program, and to VPS program schedule information. In this way, the VPS and VPT controller in the VCR can detect errors in the original schedule pages from which it was programmed, and correct for those errors in its own record programming memory. Moreover, circuitry according to the subject invention can detect an error in the VPS code of a currently-running television show, correct for the error, and properly record the show.

Abstract: A CMOS buffer amplifier can accept input signals and produce output signals that are within one half of the enhancement threshold voltage of the power supply voltages. These characteristics make this buffer amplifier ideal for use with low voltage CMOS circuitry with sub-micron geometries. The buffer amplifier contains two differential amplifiers, the output of both being combined and coupled to an output node. Each differential amplifier has matched input transducing devices on each of its inputs. One of these couples the input of the buffer amplifier to one of the inputs of the differential amplifier, while the other one couples the output of the buffer amplifier as feedback to the other side of the same differential amplifier. The pair of input transducing devices providing input to one differential amplifier are matched and suitable for operation in a higher voltage range than are the matched pair providing input to the other differential amplifier.

Abstract: A first comparison circuit compares an internally generated clock signal with a reference signal and produces a first error signal in response to timing differences between rising edges of the clock signal and the reference signal. A second comparison circuit compares the internally generated clock signal with the reference signal and produces a second error signal in response to timing differences between falling edges of the clock signal and the reference signal. The first and second error signals are applied to control inputs of a phase shifter chain to control delay in each stage to reduce the timing error with respect to each edge.

Abstract: A measuring device for the interface of a transmission path with full-duplex transmission in the common carrier duplex process. A highly integrated interface unit is connected to the interface via a hybrid set and a transmitter on one side. A line termination or a network termination is connected as the test object on the other side. In order to perform measurements on the test object with such a measuring device relatively easily and accurately, a device simulating the arrangement of a hybrid set, a transmitter and a line or network termination is provided and with its connected to the highly integrated interface unit via a high-resistance differential amplifier, and its output connected to an input of a subtractor. Another input of the subtractor is connected to the interface via an additional differential amplifier. The output of the subtractor is connected to a measurement system.

Abstract: A process for measuring the phase jitter of a data signal using a phase demodulator. To perform an accurate and relatively simple measurement of phase jitter, the data signal is supplied to a phase comparator and an auxiliary clock signal derived from a predetermined clock signal is supplied to the phase comparator via a gate circuit and a frequency divider. If the phase difference between the two signals exceeds a predetermined value, a control circuit controls the gate circuit so that the phase of the auxiliary clock signal is modified until the phase difference drops below the predetermined value. The modified auxiliary clock signal is modified again, generating a comparison clock signal which is provided to a phase modulator having an integrator so that the edge of the corresponding pulse of the data signal falls in the middle of the ramp-like output signal of the integrator when the phase jitter is zero.

Abstract: A high-frequency calibration method and circuit including a dual path step attenuator. A calibration system is provided having a switch between the user signal input and the instrument input and an amplifier between the calibration signal input and the instrument input. The amplifier provides signal conditioning. The output of the amplifier is connected to the instrument input through a switch and a resistor, the resistor isolating the switch from the instrument input so as effectively to prevent degradation of the user input signal. A sense amplifier provides a calibration signal output indicative of the input impedance of the instrument input in response to a known stimulus. The input of the sense amplifier is isolated from the instrument input by a resistor. A current source provides a known stimulus to the instrument input to measure input impedance. A step attenuator is provided having an attenuated path and an unattenuated path.

Abstract: The invention relates to a switching arrangement for connecting and/or separating two sections (7, 8) of an electrical line (3), said arrangement comprising a switching device (10) having contact elements (11, 12) which are connected to said two line sections (7, 8) as well as a plug device (15) having an actuation element (20) and plug contacts (18, 19).For providing a switching arrangement of particularly simple design for connecting and/or separating two sections of an electrical line, the present invention proposes that the contact elements (11, 12) be electrically connected to the actuation reeds of a reed contact (25) and the actuation element (20) be means magnetically influencing said reed contact which will open said reed contact (25) when the plug devide (15) is plugged in.

Abstract: A latching electrical connector with a body connectable to a receptacle and having a latch mechanism that mechanically engages the receptacle to resist disconnection. A flexible electrical cable extends from the body, and a grip element is connected to the latch mechanism to unlatch the mechanism upon pulling. The grip element is flexibly connected to the latch mechanism so that it may be folded aside to provide a compact arrangement.

Abstract: A multi-chip module development substrate (12) contains embedded test circuitry (30). Vias (38) connect I/O channels (Cn) of the test circuitry with conductive runs in interconnect layers (16,18) that are part of an interconnect structure (17) of the development substrate. Integrated circuit chips (14) are then mounted on the multi-chip module development substrate in selected electrical contact with the conductive runs. The embedded test circuitry includes multiple timing analyzer circuits (TAn) and multiple analog probe circuits en). In a preferred embodiment, these timing analyzer circuits and analog probe circuits are provided in redundant pairs, with a pair of each associated with each of the I/O channels. Multiple pairs of each kind of circuit are grouped within test cells (70) physically arranged in rectangular areas. Adjacent test circuit cells may be rotated with respect to each other to achieve more efficient connections to interconnect structure.

Abstract: A first data stream for a first data transmission system having a first data rate contains ATM data cells and structural data, which are distributed as spaced apart data in accordance with a specified instruction and are assigned to a section including in each case a plurality of ATM data cells. While retaining its ATM data cell format, the first data stream is converted into a second data stream containing only ATM data cells for a second data transmission system having a second data rate which is higher than the first data rate. The structural data are thereby selected (or picked out) from the first data stream and are input into a marked structural cell having the ATM cell format, for the section. The structural cell is inserted into the second data stream to partially fill an unoccupied section resulting from the differing data rates.