Patents Represented by Attorney Thomas J. Kilgannon, Jr.
  • Patent number: 6680758
    Abstract: The present invention relates to beam steering and scanning devices which utilize cholesteric liquid crystal (CLC) elements arranged in branches to form a logic tree. Each branch comprises an active and passive CLC element; the former further comprising a half-wave retarder and an electrode and the latter only the CLC element. Each succeeding branch contains twice as many branches as a preceding branch and, by activating active CLC element electrodes under control of a programmable pulsed source, inputs applied to the first stage of a logic tree are delivered as a scanned line of electromagnetic energy or light to the imaging cells of the last stage of the logic tree. By stacking identical logic trees with a laser source for each tree, a flat panel imaging array or display device is formed in which the transmission losses are minimized.
    Type: Grant
    Filed: January 16, 1997
    Date of Patent: January 20, 2004
    Assignee: Reveo, Inc.
    Inventor: Sadeg Mustafa Faris
  • Patent number: 5467311
    Abstract: This invention relates generally to the accessing of random access access memory arrays and, more specifically to circuits and techniques for increasing the data valid time of such memory arrays without increasing either the access or cycle times of the array. This is accomplished by providing, during a read cycle, a read signal directly to an output driver and simultaneously providing, via a parallel path, a latch output to the same driver. The latch output is provided under control of the read signal and a returning portion of a clock pulse such that the latch output overlaps the direct read signal from a read/write amplifier. An output is provided from the latch until it is reset and may last well into the next read cycle even when a new read signal is present.
    Type: Grant
    Filed: July 31, 1990
    Date of Patent: November 14, 1995
    Assignee: International Business Machines Corporation
    Inventors: Siegfried K. Wiedmann, Dieter F. G. Wendel
  • Patent number: 5459591
    Abstract: The present invention relates to beam steering and scanning devices which utilize an imaging cell which incorporates a solid-state cholesteric liquid crystal (CLC) element, an electronically controlled, variable half-wave retarder and a source of circularly polarized light. The CLC element is disposed at an angle ( relative to the path along which light from the source is projected and is designed to reflect, at a given wavelength, one circular polarization of light and transmit the other. Using this characteristic, light of one polarization or the other is presented to the variable retarder and depending on whether or not it is actuated, light is either diverted into another orthogonal path or remains in the original path. If another similar imaging cell is disposed in the orthogonal path, light incident on that cell can also be diverted into yet another path or transmitted along the orthogonal path under control of a half-wave retarders associated with said another imaging cells.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: October 17, 1995
    Inventor: Sadeg M. Faris
  • Patent number: 5364557
    Abstract: In color printing, and in the fine arts, cholesteric liquid crystal (CLC) color inks are known to possess much higher color saturation and brightness than conventional pigment and dyed based inks. However, prior art CLC ink formulations are inconvenient because in the liquid phase they have to be confined in cells, and in the solid phase, they have to be applied at high temperature, and have to be aligned by some means to produce the optimum color. This invention solves the problem encountered in the CLC prior art, by making pre-aligned CLC platelets or flakes of appropriate thickness and size and mixing them in appropriate host fluids producing a novel CLC ink which can be applied at room temperature and without the need for alignment. The new pre-aligned room temperature CLC ink can be used as a substitute for conventional inks in almost all printing and plotting, and manual drawing and painting. Using the notch filter CLC platelets, the brightness is further enhanced.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: November 15, 1994
    Inventor: Sades M. Faris
  • Patent number: 5353247
    Abstract: This application relates to a new read-write optical storage technology which is based on the cholesteric liquid crystal (CLC) polymer property of selective reflection at a characteristic wavelength. Each layer in a multi-layer CLC storage arrangement has a different characteristic wavelength, making it possible to randomly select any layer for reading, writing or erasing. Each layer incorporates a plurality of memory cells, in a write/erase mode, disposed on a dye polymer material or having such dye polymer material integrated into the CLC material such that, in the presence of light and electric or magnetic fields, the molecules of the CLC material are heated and align themselves with the electric or magnetic field. To the extent that the CLC molecules align themselves with a magnetic field normal to the plane of a storage element, electromagnetic energy in the form of light or infrared radiation at a specific wavelength, in a read mode, will be reflected.
    Type: Grant
    Filed: May 27, 1992
    Date of Patent: October 4, 1994
    Inventor: Sadeg M. Faris
  • Patent number: 5170226
    Abstract: Disclosed is a new method suitable for making highly integrated quantum wire arrays, quantum dot arrays in a single crystal compound semiconductor and FETs of less than 0.1 micron gate length. This makes it possible to construct a high-performance electronic device with high speed and low power consumption, using a combination of low-temperature-growth molecular beam epitaxy (LTG-MBE) and focused ion beam (FIB) implantation. The compound semiconductor (GaAs) epitaxial layers, which are made by LTG-MBE, are used as targets of Ga FIB implantation to make Ga wire or dot arrays. Precipitation of arsenic microcrystals, which are initially embedded in a single crystal GaAs layer and act as Schottky barriers, are typically observed in an LTG GaAs layer. A thermal annealing process, after implantation, changes the arsenic microcrystals to GaAs crystals if the arsenic microcrystals are in the region in which the Ga ions are implanted.
    Type: Grant
    Filed: May 17, 1991
    Date of Patent: December 8, 1992
    Assignee: International Business Machines Corporation
    Inventors: Tadashi Fukuzawa, Hiro Munekata
  • Patent number: 5023671
    Abstract: Quantum mechanical effect devices incorporate means for interrupting the two-dimensional carrier gas of a modulation doped structure to produce periodic potential variations which provide superlattice-like effects on current flowing nearby. The modulation doped structures incorporate specialized structures displaced from a current path which simultaneously confine the two-dimensional carrier gas into a quasi-one-dimensional carrier gas and subject the thus confined carrier gas and current flowing therein to superlattice-like effects by inducing periodic potential variations along the current path. The induced variations are produced by etching corrugations in the device edges or by forming them in biasing gates.
    Type: Grant
    Filed: March 27, 1989
    Date of Patent: June 11, 1991
    Assignee: International Business Machines Corporation
    Inventors: David P. DiVincenzo, Kim Y. Lee, Theoren P. Smith, III
  • Patent number: 4992981
    Abstract: The memory cell array is one in which the bit lines associated with each column of double-ended memory cells are interleaved with the bit lines of adjacent columns of memory cells. Because the spacing of metallic bit lines is governed by certain ground rules, cell length in the x-dimension could be reduced no further as long as metallic interconnections were used. To overcome the spacing limitation of metallic interconnections, polycrystalline fingers or extensions are substituted for metal cross-coupling interconnections. The latter in conjunction with metallic straps which are shorter than the widths and spacing of two metallic interconnection lines provides a significant reduction in the x-dimension and hence in cell area. The method and structure taught may be utilized with both bipolar and unipolar devices.
    Type: Grant
    Filed: August 24, 1989
    Date of Patent: February 12, 1991
    Assignee: International Business Machines Corporation
    Inventors: Kurt Ganssloser, Dieter F. Wendel, Siegfried K. Wiedmann
  • Patent number: 4962409
    Abstract: A field effect transistor having a highly doped gate wherein both the gate and the channel are different semiconductors with an energy band relationship that provides a barrier to both electrons and holes. The energy band relationship is staggered so that tunneling of electrons from the channel into the gate and holes from the gate into the channel is suppressed. An example structure is an InP light p conductivity type channel with a heavily doped AlInAs p.sup.++ conductivity type gate.
    Type: Grant
    Filed: February 16, 1990
    Date of Patent: October 9, 1990
    Assignee: International Business Machines Corporation
    Inventor: Paul M. Solomon
  • Patent number: 4942437
    Abstract: A quantum well type signal translating device is constructed by providing an appendage in which a reflected wave can be employed to introduce constructive or destructive interference in electron wave conduction at the heterojunction.
    Type: Grant
    Filed: January 13, 1989
    Date of Patent: July 17, 1990
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Fowler, Gregory L. Timp
  • Patent number: 4939559
    Abstract: The present invention relates to DEIS (Dual Electron Injector Structure) EAROM (Electrically Alterable Read Only Memory) devices which utilize a silicon-rich, silicon dioxide insulator between injectors which has an excess of silicon therein which is less than the excess of silicon in the silicon rich, silicon dioxide injectors. The device does not depart in any way from known DEIS EAROM devices except that the insulator layer between the injectors is rendered conductive to a desired degree by causing a compound insulator like SiO.sub.2 to be off-stoichiometry during deposition so that the resulting insulator becomes silicon rich. Alternatively, the insulator may be deposited together with another metal which renders the insulator conductive or a metallic specie may be added to the insulator by diffusion or ion implantation after the insulator is formed.
    Type: Grant
    Filed: April 1, 1986
    Date of Patent: July 3, 1990
    Assignee: International Business Machines Corporation
    Inventors: Donelli J. DiMaria, David W. Dong
  • Patent number: 4920069
    Abstract: Submicron structure fabrication is accomplished by providing vapor chemical erosion of a compound crystal by suppressing the more volatile elements so that the less volatile element is provided with an anti-agglomeration and erosion rate limiting capability which can be followed by subsequent regrowth in the same environment. The erosion is sensitive to crystallographic orientation.
    Type: Grant
    Filed: April 15, 1988
    Date of Patent: April 24, 1990
    Assignee: International Business Machines Corporation
    Inventors: Eric R. Fossum, Peter D. Kirchner, George D. Pettit, Alan C. Warren, Jerry M. Woodall
  • Patent number: 4920065
    Abstract: This invention relates generally to dynamic random access, semiconductor memory arrays and more specifically relates to an ultra dense dynamic random access memory array. It also relates to a method of fabricating such arrays using a plurality of etch and refill steps which includes a differential etching step which is a key step in forming insulating conduits which themselves are adapted to hold a pair of field effect transistor gates of the adjacent transfer devices of one device memory cells. The differential etch step provides spaced apart device regions and an insulation region of reduced height between the trenches which space apart the memory cells. The resulting structure includes a plurality of rows of vertically arranged field effect transistors wherein the substrate effectively acts as a counterelectrode surrounding the insulated drain regions of each of the one device memory cells. A pair of gates are disposed in insulating conduits which run perpendicular to the rows of memory cells.
    Type: Grant
    Filed: October 27, 1989
    Date of Patent: April 24, 1990
    Assignee: International Business Machines Corporation
    Inventors: Daeje Chin, Sang H. Dhong
  • Patent number: 4864539
    Abstract: This invention relates generally to Static Random Access Memory (SRAM) cells and more particularly, relates to a SRAM cell wherein soft-error due to .alpha.-particle radiation is reduced by permitting the potential at the common-emitter node of the cross-coupled transistors of the memory cell to swing freely. Still more particularly, it relates to a SRAM cell wherein the common-emitter node of the cell is decoupled from a heavily capacitively loaded word line with its common constant current source by means of a constant current source or current mirror disposed in each cell between the common-emitter node and the word line.
    Type: Grant
    Filed: January 15, 1987
    Date of Patent: September 5, 1989
    Assignee: International Business Machines Corporation
    Inventors: Ching-Te K. Chuang, Edward Hackbarth, Denny D. Tang
  • Patent number: 4860066
    Abstract: An environmental interface for a semiconductor electro-optical conversion device layer that is optically transparent, electrically conductive and chemically passivating, made of an elemental semiconductor with an indirect band gap>1 electron volt in a layer between 20 and 200 Angstroms thick. A GaAs covered by GaAlAs converter with a 100 Angstrom Si layer over the GaAlAs is illustrated.
    Type: Grant
    Filed: January 8, 1987
    Date of Patent: August 22, 1989
    Assignee: International Business Machines Corporation
    Inventors: Peter D. Kirchner, Ronald F. Marks, George D. Pettit, Jerry M. Woodall, Steven L. Wright
  • Patent number: 4858179
    Abstract: This invention relates generally to techniques for designing electrical circuitry and more specifically relates to a method for determining the minimum number of storage elements required to store the states of circuit. This determination is achieved by combining the output states of a circuit which occur during a pair of adjacent clock intervals into a combined state occurring during a combined clock interval. The combining step is then repeated until all possible ones of the combined states have been obtained. Still more specifically, the method includes the step of generating, prior to the combining step, a waveform pattern showing the output states of the circuit. Once the minimum number of combined states is determined, the minimum number of storage elements required can be determined by invoking the equation: m= log.sub.2 n , wherein m is the number of storage elements or memory registers and n is the sum of all possible ones of the combined states.
    Type: Grant
    Filed: November 14, 1985
    Date of Patent: August 15, 1989
    Assignee: International Business Machines Corporation
    Inventor: Shauchi Ong
  • Patent number: 4843450
    Abstract: Control of the Fermi level pinning problem and the production of flat band surface performance in compound semiconductors is achieved by providing a cationic oxide free of anionic species on the surface of the semiconductor for flat band performance and with a localized inclusion of some anionic species for barrier performance so that oxide and metal work function responsiveness is available in structure and performance in MOSFET, MESFET and different work function metal FET structures. A cationic gallium oxide is produced on GaAs by oxide growth during illumination and while being rinsed with oxygenated water. The oxidation is used to produce both anionic and cationic species while the rinsing process selectively removes all the anionic species.
    Type: Grant
    Filed: June 16, 1986
    Date of Patent: June 27, 1989
    Assignee: International Business Machines Corporation
    Inventors: Peter D. Kirchner, Alan C. Warren, Jerry M. Woodall, Steven L. Wright
  • Patent number: 4811077
    Abstract: A surface termination of a compound semiconductor is provided wherein conditions are provided for a pristine surface to be retained in an unpinned condition and a surface layer of a non-metallic material is provided. A GaAs substrate is heated in an oxygen-free atmosphere at high temperature with hydrogen sulfide, producing a pristine surface with a coating of gallium sulfide covered with a 1,000 nanometer covering of low temperature plasma enhanced chemical vapor deposited silicon dioxide.
    Type: Grant
    Filed: June 18, 1987
    Date of Patent: March 7, 1989
    Assignee: International Business Machines Corporation
    Inventors: Alan B. Fowler, John L. Freeouf, Peter D. Kirchner, Alan C. Warren, Jerry M. Woodall
  • Patent number: 4360898
    Abstract: A Programmable Logic Array (PLA) system which utilizes Josephson devices and the noninverting capabilities of these devices is disclosed. The disclosed PLA system includes a personalized Read Only Memory (ROM) which is adapted to store the applied input signals as well as the output signals which are a logic function of the input signals. As soon as outputs from the ROM are available, an interface circuit which may be timed or untimed, inverting or noninverting provides output signals which can be utilized to drive other logic circuits or to act as inputs to another personalized Read Only Memory (ROM). The latter provides another logic function of the inputs at its outputs. Again, the outputs may be used directly or applied to another interface circuit which itself may provide inverted or noninverted outputs.Like the first mentioned ROM, the second mentioned ROM is capable of storing its inputs and the resulting outputs which are some logic function of the inputs as a result of the ROM personalization.
    Type: Grant
    Filed: June 30, 1980
    Date of Patent: November 23, 1982
    Assignee: International Business Machines Corporation
    Inventor: Sadeg M. Faris
  • Patent number: 4306159
    Abstract: An inverter is disclosed which includes a fast turn-on circuit and a turn-off circuit comprising a standby current source and a parallel circuit of a diode and capacitor connected to the input of a bipolar transistor. Standby current plus an input transient applied via the charged capacitor cause high speed turn-on of the bipolar device. The diode having a lower threshold than the bipolar base-emitter diode switches when a turn-off transient is applied to the bipolar device shunting standby current which held the bipolar in the conducting state to ground via the conducting diode.
    Type: Grant
    Filed: June 14, 1979
    Date of Patent: December 15, 1981
    Assignee: International Business Machines Corporation
    Inventor: Siegfried K. Wiedmann