Patents Represented by Attorney Thomas J. Kilgannon, Jr.
  • Patent number: 4302764
    Abstract: A MOSFET which is capable of being placed in two states, one of which is quasi-stable and a memory cell which includes such a device is disclosed. The device basically consists of a pair of diffusions of one conductivity type disposed in a substrate of opposite conductivity type. The channel region between the diffusions is ion implanted or diffused with a dopant which forms a channel of the same conductivity type as the diffusions. A gate electrode is spaced from the channel region by a thin oxide and the gate and substrate are biased so that two states of the device are possible. One is a stable, equilibrium or conducting state wherein an opposite conductivity type inversion layer is formed at the surface of the now buried channel. Another state is a quasi-stable, nonequilibrium, nonconductive state wherein the channel region between the diffusions is depleted of mobile charge carriers.
    Type: Grant
    Filed: June 29, 1979
    Date of Patent: November 24, 1981
    Assignee: International Business Machines Corporation
    Inventors: Frank F. Fang, Hwa N. Yu
  • Patent number: 4291315
    Abstract: Apparatus for providing a constant density trace of an analog signal which utilizes a thermal stylus is disclosed. The minimum rise and fall times of the analog signal are of the same order of magnitude as the thermal time constant of the thermal stylus. The thermal stylus is typically controlled by a galvanometer type movement which is responsive to the variations in an analog signal. In a preferred approach, the analog signals are those obtained from electrodes connected to a human body. The thermal stylus contains a heat generating element which, in the usual situations, heats up in response to a fixed heating voltage. In the present situation, the heating element is responsive to the absolute value of the rate of change of amplitude of the analog signal.
    Type: Grant
    Filed: December 28, 1979
    Date of Patent: September 22, 1981
    Assignee: International Business Machines Corporation
    Inventor: John V. Mizzi
  • Patent number: 4274891
    Abstract: A vertical pair of complementary, bipolar transistors is disclosed which includes a semiconductor substrate of one conductivity type and a pair of dielectric isolation regions disposed in contiguous relationship with the substrate. An injector region of opposite conductivity type is disposed between the pair of isolation regions. A pair of heavily doped, polycrystalline, semiconductor regions of the one conductivity type is disposed over and in registry with the pair of isolation regions. Similarly, a single crystal, semiconductor region of the one conductivity type is disposed over and in registry with the injector region. Finally, a first zone of opposite conductivity type is disposed in the single crystal region and a second zone of the one conductivity type is disposed in the first zone.
    Type: Grant
    Filed: June 29, 1979
    Date of Patent: June 23, 1981
    Assignee: International Business Machines Corporation
    Inventors: Victor J. Silvestri, Denny D. Tang, Siegfried K. Wiedmann
  • Patent number: 4274015
    Abstract: A self-resetting digital current amplifier which utilizes Josephson devices is disclosed. The basic circuit includes a pair of switchable Josephson devices connected to each other and with an output load. The first of these devices is switched by a combination of control current and gate current. The second device is switched by a combination of gate current and current applied from an inductance which is connected between the bottom of the first Josephson device and the top of the second Josephson device. The circuit is fed by a single DC source. In the steady state, current flows from the DC source through the first of the Josephson devices to the second of the Josephson devices via the interconnecting inductance and from then back to the DC source. A pair of resistances in series with the second of the Josephson devices cause current to flow in the inductance which, in the steady state, is essentially a short circuit path.
    Type: Grant
    Filed: December 29, 1978
    Date of Patent: June 16, 1981
    Assignee: International Business Machines Corporation
    Inventor: Sadeg M. Faris
  • Patent number: 4210921
    Abstract: A polarity switch which utilizes Josephson interferometers and low drive currents is disclosed. Single ended and double ended polarity switches which are electrically the same include a pair of circuits interconnected so that the application of a pair of signals to the circuits applies a current of one polarity or the other to a utilization circuit connected to the pair of circuits. Each of the pair of circuits includes a Josephson device which carries gate current; a current path shunting the device having a transformer secondary disposed serially in the path and another Josephson device serially disposed in the same current path. The transformer secondary is coupled to a primary through which a current is passed at the outset of the memory cycle. A current is induced in the current path of one of the pair of circuits which is in opposition to the gate current flowing in the Josephson device carrying that current.
    Type: Grant
    Filed: June 30, 1978
    Date of Patent: July 1, 1980
    Assignee: International Business Machines Corporation
    Inventor: Sadeg M. Faris
  • Patent number: 4198577
    Abstract: Decoder circuit arrangements for use with Josephson memory device arrays are disclosed. In one circuit of N stages, an input circuit consists of a Josephson junction and a shunting impedance connected across the junction by means of a matched transmission line. The transmission line has two output portions each of which controls the actuation or nonactuation of a pair of devices of circuits similar to the above-described circuit which are disposed in series in a pair of branches of a serially disposed superconducting loop of a first stage. Each branch has a serially disposed address gate to which true and complement address signals are applied. Each succeeding stage is similar to the first stage except that each branch of each succeeding stage contains twice as many circuits similar to the above-mentioned first stage circuit.
    Type: Grant
    Filed: August 23, 1978
    Date of Patent: April 15, 1980
    Assignee: International Business Machines Corporation
    Inventor: Sadeg M. Faris
  • Patent number: 4182636
    Abstract: A fabrication method is disclosed for providing self-aligned (i.e., misregistration tolerant or "borderless") contact vias for electrical connections between metal interconnection lines and underlying doping semiconductive regions of an integrated circuit. The described method utilizes an oxidation barrier layer material which is patterned twice to provide, first, the recessed oxide isolation regions and, later, the self-aligned contact vias. An example of an n-channel FET embodiment is described wherein self-aligned contact vias are provided between aluminum interconnection lines and n-type doped source and drain regions. In the described method, at least a portion of the normally present misregistration region or border is eliminated between the boundary of a recessed isolation oxide and the boundary of the via. The latter is ultimately coincident with the boundary of an underlying doped region.
    Type: Grant
    Filed: June 30, 1978
    Date of Patent: January 8, 1980
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Vincent L. Rideout
  • Patent number: 4163156
    Abstract: A fabrication technique for adjusting the performance characteristics of a Josephson junction device which can be applied quickly and reliably to a large number of individual junctions, preferably using techniques adaptable to automation, is disclosed. It has been discovered that an electron beam similar to that available in electron beam processing equipment, for example, an electron microscope, can be operated in such a way as to controllably modify the electrical characteristics of a Josephson junction in a fraction of a second. Irradiation of a junction is carried out in such a way that heating of the junction to any substantial degree does not occur while the performance characteristics of a device is being modified. The fabrication conditions are well defined. To obtain modification of device characteristics, the junction thereof is subjected to an electron beam with relatively high accelerating voltage, i.e., in excess of 10 kV, and a certain radiation dosage, i.e.
    Type: Grant
    Filed: September 6, 1978
    Date of Patent: July 31, 1979
    Assignee: International Business Machines Corporation
    Inventors: Kurt Daetwyler, Rudolf Jaggi
  • Patent number: 4151605
    Abstract: A number of memory array configurations which avoid a spurious half-select condition in unselected cells of a superconducting memory array is disclosed. The memory arrays incorporate memory cells which include at least single Josephson junction disposed in a superconducting loop wherein binary information is stored in the form of at least one circulating current. By providing means for applying a control magnetic field to only the selected memory cell, spurious writing of an unselected memory cell is avoided. This is accomplished in a number of embodiments by causing the application of the half-select current (which normally provides the control magnetic field to a memory cell) to divert a previously applied half-select or enabling current to the memory cell into another path so that the previously applied half-select or enabling current now acts as a control current for switching the storage gate of the selected memory cell.
    Type: Grant
    Filed: November 22, 1977
    Date of Patent: April 24, 1979
    Assignee: International Business Machines Corporation
    Inventor: Sadeg M. Faris
  • Patent number: 4149097
    Abstract: A waveform transition sensitive Josephson junction circuit having sense bus and logic applications is disclosed. In a preferred embodiment, a device capable of carrying Josephson current is shunted by a utilization circuit. Current flowing in the device is diverted to the utilization circuit in response to only one of a pair of transitions of a pulsed input applied to the device. On one transition of the applied pulsed input current, a current is induced in a current path which follows the input until the threshold of a switchable device in the current path is exceeded. The switchable device switches and the induced current drops to zero. If the current generated by the transition is in the opposite direction to current in the Josephson device, the Josephson device remains in its unswitched state.
    Type: Grant
    Filed: December 30, 1977
    Date of Patent: April 10, 1979
    Assignee: International Business Machines Corporation
    Inventor: Sadeg M. Faris
  • Patent number: 4136290
    Abstract: A Josephson Self Gating And circuit which is powered by pulsed or clipped alternating current and provides true and complement outputs in response to true and complement inputs is disclosed. Inputs applied during the duration of the applied pulsed power or clipped alternating current are delivered to outputs which are maintained in that state in spite of a change of input within the given pulse duration. In one embodiment, the presence of an output signal interrupts a current path which, in turn, disables a pair of AND gates. These gates, even though the input to them changes, can provide no other output until the applied power falls to zero resetting the pair of AND gates which are latching in character. In another embodiment, current paths of one AND gate are cross-coupled with a current path of another AND gate.
    Type: Grant
    Filed: November 30, 1977
    Date of Patent: January 23, 1979
    Assignee: International Business Machines Corporation
    Inventors: Arthur Davidson, Dennis J. Herrell
  • Patent number: 4130893
    Abstract: A superconducting memory cell which includes a single Josephson junction or write gate disposed in a superconducting loop having improved sense margins is disclosed. The improved sense margins are achieved by fabricating the superconducting loop so that first and second branches thereof have different inductances. In a specific example, a first branch containing the single Josephson junction has the higher inductance. Still more specifically, the inductance of the first branch containing the Josephson junction or write gate is twice as great as the inductance of the other branch when the I.sub.min of the write gate is zero. In addition, another Josephson junction or sense gate must be disposed in electromagnetically coupled relationship with the second branch of the loop, and binary information must be stored in the form of clockwise and counterclockwise circulating currents of equal magnitude. Writing and reading are accomplished by coincident currents being applied to the cell.
    Type: Grant
    Filed: March 29, 1977
    Date of Patent: December 19, 1978
    Assignee: International Business Machines Corporation
    Inventor: Walter H. Henkels
  • Patent number: 4117354
    Abstract: Josephson junction interferometers having nonlinear switching or threshold characteristics are disclosed. The nonlinear threshold characteristic is achieved in a preferred manner by applying an injection current to the interferometer at a point on the interferometer which is different from where its gate current is normally applied. The resulting nonlinearity provides for high amplification. The nonlinear switching characteristic may also be achieved by applying an injection current to the same point on the interferometer where the gate current is normally applied. However, a portion of the thus-applied injection current is electromagnetically coupled to the interferometer inductance to achieve the desired nonlinear switching characteristic.
    Type: Grant
    Filed: June 30, 1977
    Date of Patent: September 26, 1978
    Assignee: International Business Machines Corporation
    Inventor: Tushar Ramesh Geewala
  • Patent number: 4117503
    Abstract: Josephson interferometers contain inductive, capacitive and resistive components, and, as a result, such devices are subject to the presence of relatively high amplitude resonances similar to those found in in-line gases. Interferometer structures exhibit the same resonant behavior as long tunnel junctions, except that there exist only as many discrete resonance voltages as meshes in the interferometer device. Hence, a two-junction interferometer has one resonance as compared to two resonances in a three-junction device. In the I-V characteristic of a Josephson tunneling device such as an interferometer, such resonances appear as current steps which must be taken into account in the design of Josephson switching circuits primarily to avoid the situation where the load line of an external load intersects a resonance peak. Where the load line and the resonance peak intersect, because such an intersection is stable, the device is prevented from switching to the full voltage desired.
    Type: Grant
    Filed: June 30, 1977
    Date of Patent: September 26, 1978
    Assignee: International Business Machines Corporation
    Inventor: Hans Helmut Zappe
  • Patent number: 4107554
    Abstract: A data bus is a common interconnection which serves as a two-way data link between inputs and outputs of several logic blocks in a time shared manner. A data bus arrangement is disclosed which can be utilized to interconnect a plurality of ports with each other and which utilize Josephson junction devices. Each of a plurality of ports represents the output from a computer or other logic circuit and these outputs represent inputs on control lines associated with each Josephson device which switch it. Each Josephson device is separately energized from its own current source and, upon switching, diverts current down a transmission line which has an impedance, Z.sub.o. In a single wire-over ground plane embodiment, all of the transmission lines are connected to a single node in a star arrangement. A terminating resistor which terminates each of the lines in a value of resistance equal to Z.sub.
    Type: Grant
    Filed: June 30, 1976
    Date of Patent: August 15, 1978
    Assignee: International Business Machines Corporation
    Inventor: Ying Luh Yao
  • Patent number: 4097765
    Abstract: An electronically alterable logic circuit is disclosed which provides different logical outputs which are a function of control signals applied to the circuit. More specifically, a non-latching Josephson junction circuit is provided which is capable of providing true and complementary outputs at a pair of output terminals when at least one pair of a plurality of pairs of fixed biases are applied to a plurality of serially arranged Josephson junction devices. The Josephson devices are arranged so that a true output can be obtained from an output circuit which shunts a pair of Josephson devices while the complement of the true output can be obtained at an output circuit which shunts an appropriately biased Josephson junction which is disposed in series with the above mentioned pair of Josephson junctions.
    Type: Grant
    Filed: June 30, 1976
    Date of Patent: June 27, 1978
    Assignee: International Business Machines Corporation
    Inventor: Hans Helmut Zappe
  • Patent number: 4092553
    Abstract: An alternating current powering arrangement for use with Josephson junction devices which have bilateral gain characteristics is disclosed. Using an alternating current input to a Josephson junction logic circuit, it is possible to carry out a desired binary logic function during one half of an alternating current cycle; reset the logic circuit; and carry out a different binary logic function during the second half of the alternating current cycle. In the instance of latching circuits, the Josephson junction logic circuits are reset by the passage of the alternating current (which is normally the gate current of the Josephson junction) through zero every half cycle. In the instance of self-resetting devices, the Josephson junctions normally reset themselves to the zero voltage state. Single phase and multiphase logic circuit powering arrangements are shown including a shift register arrangement which requires only two phases to achieve passage of information from the input to the output of the shift register.
    Type: Grant
    Filed: February 26, 1976
    Date of Patent: May 30, 1978
    Assignee: International Business Machines Corporation
    Inventors: Frank Fu Fang, Dennis James Herrell
  • Patent number: 4089061
    Abstract: A method for determining the initial values of the coefficients of a complex transversal equalizer in a synchronous data transmission system employing Double Side Band-Quadrature Carrier (DSB-QC) modulation on a transmission channel having variable distortion from message to message is disclosed. The coefficients are derived from training sequences which consist of periodic pseudo-random sequences of complex numbers having a periodic autocorrelation function, all the coefficients of which except the first are zero. The amplitude of all complex numbers of the sequence is constant. Sequences with these characteristics are identified as CAZAC sequences. With the exception of a training sequence generator and a coefficient generator the system utilized is a conventional data transmission system utilizing the DSB-QC modulation technique.
    Type: Grant
    Filed: November 18, 1976
    Date of Patent: May 9, 1978
    Assignee: International Business Machines Corporation
    Inventor: Andrzej T. Milewski
  • Patent number: 4083029
    Abstract: Contacts and resistors are provided for circuitry which are very resistant to interdiffusion and which have good stability. In particular, contacts to superconductive circuitry and resistors for superconductive circuitry are provided. In general, a contact or resistor material is in thermodynamic equilibrium with the materials which are to be contacted. Additionally, the contact or resistor is comprised of an intermediate phase or solid solution which is present in stable form in the materials to be contacted. These intermediate phases or solid solutions are multicomponent systems, such as intermetallic compounds. The contacts or resistors can be formed by layering of suitable materials and the invention can be used to provide good chip-module connections for many types of circuitry.
    Type: Grant
    Filed: July 28, 1975
    Date of Patent: April 4, 1978
    Assignee: International Business Machines Corporation
    Inventor: Syamal K. Lahiri
  • Patent number: 4075756
    Abstract: A fabrication method for integrated circuits is disclosed wherein a structure is formed on one side of a supporting substrate which provides a ground plane with "X" wiring on one side and "Y" wiring on the other side thereof. The method includes a number of alternative initial planarization steps which permits the resulting device to be substantially planar, thereby allowing it to be used as a substrate for preparation of high density integrated circuits. A first planarization step includes the deposition of a niobium thin film on a doped silicon substrate; the delineation of the desired niobium "X" wiring pattern using well-known photolithographic and etching techniques, leaving the photoresist in place to protect the niobium; the anodization of exposed silicon substrate portions to form silicon dioxide surrounding the niobium to a higher level than the niobium; and the removal of the photoresist.
    Type: Grant
    Filed: June 30, 1976
    Date of Patent: February 28, 1978
    Assignee: International Business Machines Corporation
    Inventors: Charles John Kircher, Hans Helmut Zappe