Abstract: An improved trench MOS-gated device comprises a monocrystalline semiconductor substrate on which is disposed a doped upper layer. The upper layer includes at an upper surface a plurality of heavily doped body regions having a first polarity and overlying a drain region. The upper layer further includes at its upper surface a plurality of heavily doped source regions having a second polarity opposite that of the body regions A gate trench extends from the upper surface of the upper layer to the drain region and separates one source region from another. The trench has a floor and sidewalls comprising a layer of dielectric material and contains a conductive gate material filled to a selected level and an isolation layer of dielectric material that overlies the gate material and substantially fills the trench. The upper surface of the overlying layer of dielectric material in the trench is thus substantially coplanar with the upper surface of the upper layer.

Abstract: A gate structure for a semiconductor device includes a shielding electrode and a switching electrode. Respective portions of the shielding electrode are disposed above said drain region and said well region. A first dielectric layer is disposed between the shielding electrode and the drain and well regions. The switching electrode includes respective portions that are disposed above said well region and said source region. A second dielectric layer is disposed between the switching electrode and the well and source regions. A third dielectric layer is disposed between the shielding electrode and the switching electrode.

Abstract: A power semiconductor device 10 has increased breakdown voltage due to an oxide termination structure. A peripheral trench 58 is filled with a dielectric material, such as silicon dioxide. The trench extends below the P well 22 that includes the source 32. The electric field at the border to P well 22 and trench 60 turns upward toward the surface and passes through dielectric 60. A field plate 64 coves portions of the P well 22 and the dielectric 60.

Abstract: Airbridge structures and processes for making air bridge structures and integrated circuits are disclosed. One airbridge structure has metal conductors 24 encased in a sheath of dielectric material 249. The conductors extend across a cavity 244 and a semiconductor substrate 238. In one embodiment, the conductors traversing the cavity 244 are supported by posts 248 that extend from the substrate. In another embodiment, oxide posts 258 extend from the substrate to support the conductors. In another embodiment, trenches 101 are made in a device substrate 110 bonded to a handle substrate 100. The trenches are filled with a dielectric and a conductor pattern is formed over the filled trenches. The substrate material between the conductors is then removed to leave a pattern of posts 116, 114, 112 that included dielectrically encased conductors 106. In another bonded wafer embodiment, conductors 204 are encased in a dielectric above a sacrificial device region.

Abstract: A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.

Abstract: An MOS power device a substrate comprises an upper layer having an upper surface and an underlying drain region, a well region of a first conductance type disposed in the upper layer over the drain region, and a plurality of spaced apart buried gates, each of which comprises a trench that extends from the upper surface of the upper layer through the well region into the drain region. Each trench comprises an insulating material lining its surface, a conductive material filling its lower portion to a selected level substantially below the upper surface of the upper layer, and an insulating material substantially filling the remainder of the trench. A plurality of highly doped source regions of a second conductance type are disposed in the upper layer adjacent the upper portion of each trench, each source region extending from the upper surface to a depth in the upper layer selected to provide overlap between the source regions and the conductive material in the trenches.

Abstract: A first thin film resistor formed by direct etch or lift off on a first dielectric layer that covers an integrated circuit in a substrate. A second thin film resistor comprised of a different material than the first resistor, formed by direct etch or lift off on the first dielectric layer or on a second dielectric layer over the first dielectric layer. The first and second thin film resistors are interconnected with another electronic device such as other resistors or the integrated circuit.

Abstract: Semiconductor structures such as the trench and planar MOSFETs (UMOS), trench and planar IGBTs and trench MCTs using trenches to establish a conductor. Improved control of the parasitic transistor in the trench MOSFET is also achieved and cell size and pitch is reduced relative to conventional structures.

Abstract: A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the substrate in the upper layer comprises two segments having differing widths relative to one another: a bottom segment of lesser width filled with a dielectric material, and an upper segment of greater width lined with a dielectric material and substantially filled with a conductive material, the filled upper segment of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from an upper surface into the upper layer of the substrate only on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench.

Abstract: A radiation hardening isolation technique uses a poly buffered LOCOS structure (34, 36) to protect the device areas during field oxide 40 formation. The field oxide 40 is removed, and the polysilicon structure 34 is covered with a PSG or BPSG layer 42. Layer 42 is planarized and the polysilicon 34 is removed to provide a self-aligned device region 31.

Abstract: The planarity of semiconductor device pins is measured simultaneously by multiple pneumatic comparator circuits by detecting pressure changes proportional to pin position.

Abstract: A flip-flop circuit has two D type flip-flops. A common system clock drives both flip-flops. A stream of asynchronous data is connected to the data input of the first flip-flop FF1. The output of FF1 is connected to the data input of the second flip-flop FF2. The timing characteristics of FF1 and FF2 are chosen so that the time from the clock pulse to the high logic output of FF1 plus the set up time of FF2 is less than the minimum propagation delay time of FF2.

Abstract: A signed digit adder (10) includes a plurality of cells (12) which input signals X.sub.s, X.sub.m, Y.sub.s, Y.sub.m, R.sub.-1 and U.sub.-1, where X.sub.s and X.sub.m are the sign and magnitude bits of one digit of a signed bit representation. Similarly, Y.sub.s and Y.sub.m are the sign and magnitude bits of the second operand. R.sub.-1 and U.sub.-1 are signals received from the preceding cell (12). Each cell outputs R and U bits, and the sum bits Z.sub.s and Z.sub.m. Each cell (12) comprises function blocks (14-26) which determine the outputs from the given inputs. Function block (14) determines the output R as NOT(X.sub.s +Y.sub.s). Function block (20) determines the output U=E.multidot.NOT(R.sub.-1)+NOT(E).multidot.NOT(Q) where Q=(NOT (X.sub.s)+NOT (Y.sub.s)).multidot.X.sub.m. The determination of Q is performed in function block (16). Function block (24) determines the output Z.sub.s =U.sub.-1 .multidot.T and function block (26) determines the output Z.sub.m =U.sub.-1 XOR (NOT (T)).

Abstract: The disclosure relates to a cache memory formed on a single chip wherein the ability to test the address comparator, cache memory diagnostics are improved, cache memory are capable of being read out. The architecture comprises a parity generator, a parity checker, a comparator and an SRAM memory call array. The cache memory is cascadable for access to an increased address range and to provide increased memory capacity.

Abstract: A CCD imager (10) is adaptable for recording a still image and translating the still image into a NTSC television format. An image array (12) of the imager (10) has a plurality of cells arranged in rows and columns (35-37). The cells are further divided into a plurality of fields including a first field and a second field, cells in any one row belong to a single field. A memory array (16) of the imager comprises a plurality of memory cells (128, 130, 82, 84, 174, 176, 152 and 154) including first cells (128, 82, 174, 152) for storing signals from the first field, and second cells (130, 84, 176, 54) for storing signals from the second field. A transferor (14) is operable to transfer the first field signals to the first memory cells (128, 174, 152), and also transfers the second field signals to the second memory cells (130, 84, 176, 154).

Abstract: A metal stud (24) is provided for interconnecting levels of metallization separated by an insulator on a semiconductor slice (10). A lead (12) is coated with a refractory metal (14) and a platable metal cap (16). A photoresist (18 ) is then applied and a cavity (22) is formed within the photoresist (18 ). The cavity (22) is plated to form the stud (24). The stud (24) is clad with a corrosion resistant layer (28).

Abstract: A method of testing circuitry is by the application of scan design which consists of a series of shift registers or latches which form a serial scan path through a logic circuit. The scan path can be used to observe and control logic elements in the design via serial scan operations. The present invention allows a continuous scan path to be compressed or expanded so that the scan path only passes through the desired logic element(s) to be tested. Devices connected on the serial scan path (or ring) can be selected or deselected thus allowing the serial path to either flow through or bypass a given logic circuit's internal scan path. The invention can be used to create a hierarchical scan network consisting of a primary scan ring from which a multiplicity of scan sub-rings may be accessed.

Abstract: A first-in, first-out memory has a write pointer (34) that includes a higher-order ring counter (192) and a lower-order ring counter (190). Ring counters (190, 192) store respective higher-order and lower-order address digits that are together used to select one of a plurality of write select gates (202). Each gate (202) is operable to both power up and address is coupled to a respective memory word location. A read pointer (28) of the FIFO has an analogous architecture. The lower-order and higher-order address digits generated by the write and read pointers (34 and 28) are used by a pointer comparator (44) to generate a plurality of intermediate signals. The intermediate signals are in turn received by a flag decoder (52) that generates EMPTY, FULL, ALMOST-FULL/EMPTY, and HALF-FULL status flags. A write-read control section (48) of the FIFO has a pair of monostable multivibrators (68, 82) that generate write and read clock pulses of a uniform pulse width.

Abstract: A circuit for resetting a multi-bit word in a digital memory at a selected address receives a word reset signal to cause entry into the selected address of a multi-bit word wherein all the bits are set to the same level and a parity bit is set to a value corresponding to parity in the multi-bit word. The circuit includes a parity generator which receives a multi-bit input data word and generates at least one parity bit therefrom. During a normal write operation, the multi-bit input data word and the parity bit are written into the digital memory at the selected address. During a word reset signal, output from the parity generator and the multi-bit input data word are blocked from entry into the memory.

Abstract: Test logic may be included in the design of an integrated circuit (IC) to facilitate testability. In most instances, an IC's test logic can only be activated while the IC, or logic sections within the IC, are placed in a non-functional test mode. The present invention is directed toward an event qualification structure providing the timing and control required to activate an IC's test logic during normal functional operation.