Patents Represented by Attorney, Agent or Law Firm Tiffany L. Townsend
  • Patent number: 6816517
    Abstract: An arrangement for tuning a micro-electro-mechanical (MEM) laser center wavelength to exactly match the passband of its associated filter. A dither wavelength locked feedback loop dynamically adjusts the position of the MEM element, and hence the laser, wavelength, to keep it nominally centered at the filter passband peak. The dither wavelength locked feedback loop compensates for many internal variables of the laser, filter, and the MEM with a single mechanism that stabilizes the laser and locks the wavelength to any desired value.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: November 9, 2004
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Jacobowitz, Casimer M. DeCusatis
  • Patent number: 6790125
    Abstract: A method for preparing a semiconductor die for analysis comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, providing a rotatable spindle for securing the polishing pad, and providing a constant force actuator on the spindle, the constant force actuator being adapted to provide constant force between the polishing pad and the backside surface of the die. The method then includes contacting the backside die surface with the polishing pad, rotating the spindle and polishing pad, and polishing the backside surface of the die while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: September 14, 2004
    Assignee: International Business Machines Corporation
    Inventors: Terence Kane, Darrell L. Miles
  • Patent number: 6787783
    Abstract: A method and apparatus for editing an integrated circuit by bombarding a feature in need of editing with either a low-energy or high-energy electron beam in the presence of a gas whereby low energy electrons activate reactants adsorbed on the surface of the feature in need of editing to form active species on the feature surface. The reaction products from the process can be easily removed whereby IC damage, leakage between metal features, wafer contamination and physical sputtering of undesired material can be significantly minimized while still possessing nanometer-scale spatial resolution. The low energy electrons for activating the reactants adsorbed on the surface of the feature to be edited may be emitted from the electron beam itself or they may be secondary low energy is electrons emitted from the surface of the feature being edited.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: September 7, 2004
    Assignee: International Business Machines Corporation
    Inventors: Herschel M. Marchman, Aaron D. Shore
  • Patent number: 6766211
    Abstract: The amplification of target overlay errors of interleaved arrays in semiconductor fabrication is achieved by calculating the synthesized beat signal on a set of targets that are imaged using conventional microscopy and measured using a geometrical image processing algorithm. The interleaved arrays have differing periodicities resulting in a phase shift. The difference in periodicity distinguishes the arrays and amplifies the sensitivity to the overlay error. The phase-shift ensures that the elements of the arrays are interleaved and not overlapped. The beat signal has a zero crossing location that is proportional to the overlay error between the interleaved arrays, with a proportionality constant much greater than one. The overlay error is amplified by this proportionality constant. In an alternative embodiment, the geometrical image processing algorithm is first digitally filtered prior to obtaining the overlay error. This spatial filtering allows for noise suppression.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: July 20, 2004
    Assignee: International Business Machines Corporation
    Inventor: Christopher P. Ausschnitt
  • Patent number: 6751014
    Abstract: A system and method for controlling alignment of laser center wavelengths and filter passband center wavelengths in optical amplifiers for purposes of providing automatic gain control and eliminating unwanted noise. The system and method exploits a wavelength-locked loop servo-control circuit and methodology that enables real time mutual alignment of a laser pump signal having a peaked spectrum function including a center wavelength and a wavelength selective device such as an optical filter implementing a peaked passband function including a center wavelength in an optical amplifier.
    Type: Grant
    Filed: June 19, 2001
    Date of Patent: June 15, 2004
    Assignee: International Business Machines Corporation
    Inventors: Casimer M. DeCusatis, Lawrence Jacobowitz
  • Patent number: 6738187
    Abstract: A system and method for improving optical signal gain efficiencies of semiconductor optical amplifier devices. The system and method exploits a wavelength-locked loop servo-control circuit and methodology that enables real time mutual alignment of the center wavelength of an optical signal having a peaked spectrum function and transmitted through the semiconductor optical amplifier, and a center wavelength of a wavelength selective device such as an optical filter implementing a peaked passband function in an optical system. The wavelength-locked loop servo-control circuit and methodology may be further exploited to control various types of modulation applied to the optical signals transmitted in optical systems.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: May 18, 2004
    Assignee: International Business Machines Corporation
    Inventors: Casimer Maurice DeCusatis, Lawrence Jacobowitz
  • Patent number: 6730529
    Abstract: Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exposed vias. This metal layer and the insulator layer covering the other buried vias are removed after testing to re-establish the full via set. As an extension to this basic test process, test circuits can be formed around or beside the chip to be tested in the kerf areas separating the chip from other chips on the semiconductor wafer. Connections to the test circuits is with a sacrificial metal layer over an insulator layer. The sacrificial metal layer and insulator layer are removed after testing.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: May 4, 2004
    Assignee: International Business Machines Corporation
    Inventors: Howard L. Kalter, H. Bernhard Pogge, George S. Prokop, Donald L. Wheater
  • Patent number: 6724786
    Abstract: A system and method for automatically attenuating optical signals transmitted in optical systems. The system and method exploits a wavelength-locked loop servo-control circuit and methodology that enables real time mutual alignment of the center wavelength of an optical signal having a peaked spectrum function and transmitted through the optical system, and a center wavelength of a wavelength selective device such as an optical filter element implementing a peaked passband function. The wavelength-locked loop servo-control circuit and methodology particularly is capable of real-time aligning the center wavelength of an optical signal in a range between maximum overlap with the center wavelength of the peaked passband function of the optical filter for maximum transfer of output optical signal by the filter element and minimum overlap with the peaked passband function of the optical filter so that output optical signal may be attenuated in the optical system.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: April 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Jacobowitz, Casimer Maurice DeCusatis
  • Patent number: 6724203
    Abstract: A semi-conductor wafer test or burn-in apparatus having spring contacts made from a shape memory metal which plastically deforms under normal test loading and has a transition temperature at or above or at or below the burn-in temperature.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: April 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: Lewis S. Goldmann, Chandrika Prasad
  • Patent number: 6720630
    Abstract: A method of forming a metal oxide semiconductor field effect transistor (MOSFET) having a metallic gate electrode that is protected with hanging sidewall spacers during a subsequent gate oxidation process is provided. A semiconductor structure formed by the inventive method is also provided. Specifically, the inventive semiconductor structure includes a semiconductor substrate comprising a patterned gate region formed atop a patterned gate dielectric, the patterned gate region includes at least a metallic gate electrode formed atop a polysilicon gate electrode; hanging sidewall spacers formed on an upper portion of the patterned gate region including the metallic gate electrode; and a thermal oxide layer formed on lower portions of patterned gate region including a portion of the polysilicon gate electrode, but not the metallic gate electrode.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: April 13, 2004
    Assignee: International Business Machines Corporation
    Inventors: Jack A. Mandelman, Oleg Gluschenkov, Carl J. Radens
  • Patent number: 6693041
    Abstract: A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically aligned to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: February 17, 2004
    Assignee: International Business Machines Corporation
    Inventors: Ramachandra Divakaruni, Jack A. Mandelman, Carl J. Radens
  • Patent number: 6689629
    Abstract: Disclosed is to provide an array substrate for display, a method of manufacturing the array substrate for display and a display device using the array substrate for display. The present invention is an array substrate for display, which includes: a thin film transistor array formed on an insulating substrate 1; a plurality of wirings 23 and 24 arranged on the insulating substrate 1; connection pads 25 and 27 arranged on unilateral ends of the wirings 23 and 24 and respectively connected therewith; and pixel electrodes 22, wherein dummy conductive patterns 29 are arranged between the ends of the connection pads 25 and 27 and ends of the pixel electrodes 22.
    Type: Grant
    Filed: February 5, 2002
    Date of Patent: February 10, 2004
    Assignee: International Business Machines Corporation
    Inventors: Takatoshi Tsujimura, Atsuya Makita, Toshiaki Arai
  • Patent number: 6674936
    Abstract: A system and method of compensating for optical polarization dispersion effects exhibited in a length of optical fiber in an optical network. The system and method exploits a wavelength-locked loop servo-control circuit and methodology that detects a polarization mode dispersion characteristic of the optical signal and enables real time adjustment of the center wavelength of the optical in manner so as to minimize polarization effects in the optical fiber link. In another embodiment, the wavelength-locked loop servo-control circuit and methodology is implemented for enabling real time physical adjustment, e.g., X-Y dimension strain control, of the optical fiber link itself in accordance with the detected amount of polarization mode dispersion.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: January 6, 2004
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Jacobowitz, Casimer Maurice DeCusatis
  • Patent number: 6654152
    Abstract: Wavelength locked feedback loops are provided in frequency guide filters, and particularly in sliding frequency guide filters, wherein the wavelength locked feedback loop allows precise control over the location of the filter center wavelength with respect to a transmitted soliton center wavelength, compensating for factors such as the filter rolloff, signal spectral width, and changes in the transmission line properties due to temperature, microbending, aging and other effects. This approach allows the construction of very inexpensive frequency guiding filters, which can be based on low precision frequency domain filters with active compensation. These advantages make it possible to design new types of dispersion managed soliton optical transmission networks.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: November 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Jacobowitz, Casimer M. DeCusatis
  • Patent number: 6630074
    Abstract: An aqueous etchant composition containing about 0.01 to about 15 percent by weight of sulfuric acid and about 0.01 to about 20 percent by weight of hydrogen peroxide or about 1 to 30 ppm of ozone, and about 0.01 to 100 ppm of hydrofluoric acid is effective in removing polymer and via residue from a substrate or conductive material, and especially from an integrated circuit chip having aluminum lines thereon.
    Type: Grant
    Filed: August 20, 1998
    Date of Patent: October 7, 2003
    Assignee: International Business Machines Corporation
    Inventors: David Lee Rath, Ravikumar Ramachandran
  • Patent number: 6629363
    Abstract: A process for picking up and moving a microelectronic package during card assembly operations. A clipping lid having a top surface and at least two sides attaches to a substrate via friction where the sides act as leaf springs gripping the substrate. The top surface of the lid provides a clean, smooth, flat surface to which a vacuum probe may be attached. In the preferred embodiment, the lid and sides are formed from an integral piece of stainless steel. Also provided are flares at the bottom of each side to aid in guiding the lid onto the substrate. Protrusions are provided in the sides to prevent the lid from slipping too far onto the substrate and contacting the components mounted to the substrate. Also provided is at least one hole in the top surface to allow the lid to be pried free from the substrate after completion of the steps where vacuum probe movement is required.
    Type: Grant
    Filed: January 22, 1998
    Date of Patent: October 7, 2003
    Assignee: International Business Machines Corporation
    Inventor: Joseph Ying-Yuen Chan
  • Patent number: 6613484
    Abstract: A method for maintaining critical dimension during the etching of dielectrics, having the following steps: depositing a layer of photoresist over a layer of dielectric; patterning the photoresist such that voids are formed in the photoresist, the voids having sidewalls and a bottom; depositing an overlayer in an etch chamber; transferring the patterning in the photoresist to the dielectric.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: September 2, 2003
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Dalton, Bernd E. E. Kastenmeier, Theodorus E. Standaert
  • Patent number: 6611146
    Abstract: An apparatus for applying a stress voltage to a device under test includes a stress voltage source, a constant voltage circuit having an input connected to the stress voltage source and an output connected to a control circuit for removing stress when current exceeds a predetermined level which is connected to the device under test. The constant voltage circuit provides a constant stress voltage to the device under test. A monitoring circuit measures the stress voltage applied to the device under test, and measures leakage current through the device under test. A switch has inputs connected to outputs of the monitoring circuit, with the switch being capable of sending a selected output or outputs of the monitoring circuit to a measurement system.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: August 26, 2003
    Assignee: International Business Machines Corporation
    Inventor: Charles J. Montrose
  • Patent number: 6605838
    Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: August 12, 2003
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corporation
    Inventors: Jack A. Mandelman, Rama Divakaruni, Gerd Fehlauer, Stephan Kudelka, Uwe Schroeder, Helmut H. Tews
  • Patent number: 6602772
    Abstract: An apparatus and method for evaluating the performance of a test dielectric material for use as a gate dielectric. The method comprises exposing a coated layer of the dielectric to a concentration of atomic hydrogen. The method may comprise (a) measuring an initial value of interface-state density in the test dielectric, (b) exposing the coated test dielectric to a concentration of atomic hydrogen in a remote plasma, and then (c) measuring a post-exposure value of interface-state density in the test dielectric. Steps (b) and (c) may be repeated with incrementally higher concentrations of atomic hydrogen to determine a rate of change in interface-state density value as a function of atomic hydrogen concentration, which may then be related to the projected charge-to-breakdown or time-to-breakdown of the test dielectric layer when the dielectric is used as the gate dielectric.
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: August 5, 2003
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Eduard A. Cartier, James H. Stathis