Abstract: A method for preparing a semiconductor die for analysis comprises providing a semiconductor die having a connector on one side and an opposite, backside surface to be analyzed, providing a polishing pad for polishing the backside surface of a semiconductor die, providing a rotatable spindle for securing the polishing pad, and providing a constant force actuator on the spindle, the constant force actuator being adapted to provide constant force between the polishing pad and the backside surface of the die. The method then includes contacting the backside die surface with the polishing pad, rotating the spindle and polishing pad, and polishing the backside surface of the die while maintaining the substantially constant force of the polishing pad on the die backside surface with the constant force actuator.

Abstract: A method and apparatus for editing an integrated circuit by bombarding a feature in need of editing with either a low-energy or high-energy electron beam in the presence of a gas whereby low energy electrons activate reactants adsorbed on the surface of the feature in need of editing to form active species on the feature surface. The reaction products from the process can be easily removed whereby IC damage, leakage between metal features, wafer contamination and physical sputtering of undesired material can be significantly minimized while still possessing nanometer-scale spatial resolution. The low energy electrons for activating the reactants adsorbed on the surface of the feature to be edited may be emitted from the electron beam itself or they may be secondary low energy is electrons emitted from the surface of the feature being edited.

Abstract: The amplification of target overlay errors of interleaved arrays in semiconductor fabrication is achieved by calculating the synthesized beat signal on a set of targets that are imaged using conventional microscopy and measured using a geometrical image processing algorithm. The interleaved arrays have differing periodicities resulting in a phase shift. The difference in periodicity distinguishes the arrays and amplifies the sensitivity to the overlay error. The phase-shift ensures that the elements of the arrays are interleaved and not overlapped. The beat signal has a zero crossing location that is proportional to the overlay error between the interleaved arrays, with a proportionality constant much greater than one. The overlay error is amplified by this proportionality constant. In an alternative embodiment, the geometrical image processing algorithm is first digitally filtered prior to obtaining the overlay error. This spatial filtering allows for noise suppression.

Abstract: Large area chip functionality is tested at an intermediate level in the manufacturing process. A process sequence is implemented in which a layer of insulator material is deposited over the chip. This layer is then processed to selectively open areas over existing vias which are to be used for chip level testing. The other vias remain covered with insulator. A sacrificial metal level is then deposited on the insulator layer and patterned to create adequately large test pad areas connected to exposed vias. This metal layer and the insulator layer covering the other buried vias are removed after testing to re-establish the full via set. As an extension to this basic test process, test circuits can be formed around or beside the chip to be tested in the kerf areas separating the chip from other chips on the semiconductor wafer. Connections to the test circuits is with a sacrificial metal layer over an insulator layer. The sacrificial metal layer and insulator layer are removed after testing.

Abstract: A self-aligned shallow trench isolation region for a memory cell array is formed by etching a plurality of vertical deep trenches in a substrate and coating the trenches with an oxidation barrier layer. The oxidation barrier layer is recessed in portions of the trenches to expose portions of the substrate in the trenches. The exposed portions of the substrate are merged by oxidization into thermal oxide regions to form the self-aligned shallow trench isolation structure which isolates adjacent portions of substrate material. The merged oxide regions are self-aligned as they automatically aligned to the edges of the deep trenches when merged together to define the location of the isolation region within the memory cell array during IC fabrication. The instant self-aligned shallow trench isolation structure avoids the need for an isolation mask to separate or isolate the plurality of trenches within adjacent active area rows on a single substrate.

Abstract: Disclosed is to provide an array substrate for display, a method of manufacturing the array substrate for display and a display device using the array substrate for display. The present invention is an array substrate for display, which includes: a thin film transistor array formed on an insulating substrate 1; a plurality of wirings 23 and 24 arranged on the insulating substrate 1; connection pads 25 and 27 arranged on unilateral ends of the wirings 23 and 24 and respectively connected therewith; and pixel electrodes 22, wherein dummy conductive patterns 29 are arranged between the ends of the connection pads 25 and 27 and ends of the pixel electrodes 22.

Abstract: Wavelength locked feedback loops are provided in frequency guide filters, and particularly in sliding frequency guide filters, wherein the wavelength locked feedback loop allows precise control over the location of the filter center wavelength with respect to a transmitted soliton center wavelength, compensating for factors such as the filter rolloff, signal spectral width, and changes in the transmission line properties due to temperature, microbending, aging and other effects. This approach allows the construction of very inexpensive frequency guiding filters, which can be based on low precision frequency domain filters with active compensation. These advantages make it possible to design new types of dispersion managed soliton optical transmission networks.

Abstract: An aqueous etchant composition containing about 0.01 to about 15 percent by weight of sulfuric acid and about 0.01 to about 20 percent by weight of hydrogen peroxide or about 1 to 30 ppm of ozone, and about 0.01 to 100 ppm of hydrofluoric acid is effective in removing polymer and via residue from a substrate or conductive material, and especially from an integrated circuit chip having aluminum lines thereon.

Abstract: A method for maintaining critical dimension during the etching of dielectrics, having the following steps: depositing a layer of photoresist over a layer of dielectric; patterning the photoresist such that voids are formed in the photoresist, the voids having sidewalls and a bottom; depositing an overlayer in an etch chamber; transferring the patterning in the photoresist to the dielectric.

Abstract: An apparatus for applying a stress voltage to a device under test includes a stress voltage source, a constant voltage circuit having an input connected to the stress voltage source and an output connected to a control circuit for removing stress when current exceeds a predetermined level which is connected to the device under test. The constant voltage circuit provides a constant stress voltage to the device under test. A monitoring circuit measures the stress voltage applied to the device under test, and measures leakage current through the device under test. A switch has inputs connected to outputs of the monitoring circuit, with the switch being capable of sending a selected output or outputs of the monitoring circuit to a measurement system.

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 &mgr;m or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

Abstract: A system and method for precisely controlling the wavelength selective function provided by fiber Bragg gratings in optical fiber elements. The system and method exploits a wavelength-locked loop servo-control circuit and methodology that enables real time adjustment of the grating pattern being written to said fiber optical link element by a grating writing source to thereby mutually align a center wavelength of the peaked wavelength selective function resulting from the grating pattern with a center wavelength of the optical signal transmitted over a communication channel provided by the fiber. A real-time adaptive dispersion compensation technique for optical fibers is additionally provided that exploits the wavelength-locked loop servo-control circuit.

Abstract: Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt.

Abstract: A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.

Abstract: A method of processing greensheets, wherein the following steps are performed: a) providing a greensheet having a width, length, thickness, a first side and a second side; b) bonding to the first side of the greensheet at least one strip, wherein the strip lies in a first plane; c) bonding to the second side of the green sheet at least one strip, wherein the strip lies in a second plane; d) processing the greensheet; and e) removing the strips from the processed greensheet.

Abstract: An apparatus is described for detecting the presence of a gaseous chemical produced during a chemical-mechanical polishing operation. The apparatus includes a catalytic converter, a reaction chamber and a light sensor. The catalytic converter, heated to about 800° C. converts the chemical to a different chemical product. The reaction chamber produces an excited species; the pressure in the reaction chamber is maintained sufficiently low to substantially avoid collisional deactivation of the excited species, so as to permit real-time detection of the chemical. A light signal from the excited species is input to the light sensor. An output from the light sensor corresponds to the real-time detection of the chemical, thereby permitting real-time control of the chemical-mechanical polishing operation.

Abstract: A semiconductor interconnect connection mechanism for attaching individual surface mounted semiconductor objects to multichip products whereby at least a portion of the electrical pathway between different objects on the top surface of surface mounted devices is not located on the top surface.

Abstract: A heat sink assembly and method for attaching a multi-chip module cap to a polymeric heat sink adhesive by means of a thin adhesion-promoting metal film layer, which provides an interfacial bond between the cap and polymeric adhesive meeting package performance and reliability requirements. There is also a method of promoting adhesion between a silicon-containing polymeric adhesive and a metal surface using the thin adhesion-promoting metal film layer and the products thereof.

Abstract: A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.

Abstract: The method of the present invention applies to any semiconductor structure provided with polysilicon filled deep trenches formed in a silicon substrate coated by a Si3N4 pad layer both in the “array” and “kerf” areas. First, a photoresist mask is formed onto the structure and patterned to expose the deep trenches only in the “array” areas. Deep trenches are then anisotropically dry etched to create recesses having a determined depth. Next, the photoresist mask is removed only in the “array” areas. A step of anisotropic dry etching is now performed to extend said recesses down to the desired depth to create the shallow isolation trenches. The photoresist mask is totally removed. A layer of oxide (STI oxide) is conformally deposited by LPCVD onto the structure to fill said shallow isolation trenches in excess. The structure is planarized to create the STI oxide regions and expose deep trenches in the “kerf” areas.