Abstract: A system and method for precisely controlling the wavelength selective function provided by fiber Bragg gratings in optical fiber elements. The system and method exploits a wavelength-locked loop servo-control circuit and methodology that enables real time adjustment of the grating pattern being written to said fiber optical link element by a grating writing source to thereby mutually align a center wavelength of the peaked wavelength selective function resulting from the grating pattern with a center wavelength of the optical signal transmitted over a communication channel provided by the fiber. A real-time adaptive dispersion compensation technique for optical fibers is additionally provided that exploits the wavelength-locked loop servo-control circuit.

Abstract: A system for stressing and monitoring an electrical device, such that the imposed stress conditions may be terminated at electronic speeds, thereby preventing destruction of the device under test. The system includes stress channels each paired with a control and monitor circuit, such that the control and monitor circuit may shut down the stress if a limiting stress level is detected by the control and monitor circuit. A microprocessor is used to communicate via a digital control bus with each of the paired stress channels and control and monitor circuits to determine the status of the stress channel; control the stress input; and enable or disable the control and monitor circuits. A computer is used to communicate with the microprocessor through a serial interface.

Abstract: Metal oxide semiconductor field effect transistor (MOSFET) comprising a drain region and source region which enclose a channel region. A thin gate oxide is situated on the channel region and a gate conductor with vertical side walls is located on this gate oxide. The interfaces between the source region and channel region and the drain region and channel region are abrupt.

Abstract: A method of creating a pattern for a mask adapted for use in lithographic production of features on a substrate. The method comprises initially providing a mask pattern of a feature to be created on the substrate using the mask. The method then includes establishing target dimensional bounds of the pattern, determining simulated achievable dimensional bounds of the pattern, comparing the target dimensional bounds of the pattern to the simulated achievable dimensional bounds of the pattern, and determining locations where the simulated achievable dimensional bounds of the pattern differ from the target dimensional bounds of the pattern. In its preferred embodiment, the feature is an integrated circuit to be lithographically produced on a semiconductor substrate.

Abstract: A method of processing greensheets, wherein the following steps are performed: a) providing a greensheet having a width, length, thickness, a first side and a second side; b) bonding to the first side of the greensheet at least one strip, wherein the strip lies in a first plane; c) bonding to the second side of the green sheet at least one strip, wherein the strip lies in a second plane; d) processing the greensheet; and e) removing the strips from the processed greensheet.

Abstract: An apparatus is described for detecting the presence of a gaseous chemical produced during a chemical-mechanical polishing operation. The apparatus includes a catalytic converter, a reaction chamber and a light sensor. The catalytic converter, heated to about 800° C. converts the chemical to a different chemical product. The reaction chamber produces an excited species; the pressure in the reaction chamber is maintained sufficiently low to substantially avoid collisional deactivation of the excited species, so as to permit real-time detection of the chemical. A light signal from the excited species is input to the light sensor. An output from the light sensor corresponds to the real-time detection of the chemical, thereby permitting real-time control of the chemical-mechanical polishing operation.

Abstract: A semiconductor interconnect connection mechanism for attaching individual surface mounted semiconductor objects to multichip products whereby at least a portion of the electrical pathway between different objects on the top surface of surface mounted devices is not located on the top surface.

Abstract: A semiconductor device having a planar integrated circuit interconnect and process of fabrication. The planar integrated circuit comprises a substrate having a first line wire formed in the substrate, a dielectric layer formed on the substrate, a second line wire formed in the dielectric layer, a contact via formed within the dielectric layer extending through the dielectric layer from the second line wire to the first line wire, and a dummy via which extends into the dielectric layer and is filled with a low dielectric material.

Abstract: A process for obtaining accurate DC convergence in a DC phase of a circuit simulation program for models of field effect transistors (FETs) on a silicon-on-insulator (SOI) substrate. The process comprises running iterations of the DC phase of the circuit simulation program such that error criteria are satisfied, wherein the pseudo-time step changes at each iteration until it reaches a value such that a desired current value is achieved. DC convergence is also achieved by reducing the magnitude of the capacitive and/or charge elements connected to the floating body regions of the field effect transistors on the silicon-on-insulator substrate model during the DC phase to achieve a desired current value.

Abstract: A heat sink assembly and method for attaching a multi-chip module cap to a polymeric heat sink adhesive by means of a thin adhesion-promoting metal film layer, which provides an interfacial bond between the cap and polymeric adhesive meeting package performance and reliability requirements. There is also a method of promoting adhesion between a silicon-containing polymeric adhesive and a metal surface using the thin adhesion-promoting metal film layer and the products thereof.

Abstract: A fixture for holding a workpiece in a machining apparatus comprises at least one opening having at least one flexible side for elastically holding the workpiece and a slot adjacent each of the at least one side for allowing the side to flex.

Abstract: A trench capacitor having an increased surface area. In one embodiment, the trench capacitor is a dual trench capacitor having a first trench and a second trench wherein inner walls of the trenches electrically connect. The invention also includes a single trench capacitor wherein the trench is curved around an axis substantially perpendicular to a substrate surface.

Abstract: A stress-driver circuit for providing a constant voltage (Vce) and a constant current (I=Vin/R) to a bipolar transistor under test. The circuit includes a power source, an op-amp, a FET, and the bipolar transistor. The power source is connected to the bipolar transistor collector. The op-amp has a positive input biased at input voltage (Vin) and a negative input having a feedback loop connected to the bipolar transistor emitter. The op-amp output is connected to the FET gate, the FET drain is connected to the power supply, and the FET source is biased to ground through a first resistor and connected to the base of the bipolar transistor. The second resistor is connected at one end to the bipolar transistor emitter and biased to ground at the other end. An automatic trip circuit may be provided to cut off power to the bipolar transistor if the current at the bipolar transistor collector exceeds a predetermined value.

Abstract: A bed-of-nails type or needle-card type test probe has clusters of parallel buckling beams arranged in a spaced arrangement. The buckling beams are arranged and electrically connected within a cluster so that a contaminant, which may be on the device being tested, does not reduce the accuracy of the test measurements. In particular, the spacing of the buckling beams is such that multiple buckling beams are capable of contacting a single feature on an electronics package to be tested. The buckling beams deflect independently of each other in response to compressive force, and the buckling beams within a cluster are electrically connected in parallel to each other to define redundant, independent conductive paths through the buckling beams. In this way, if a contaminant prevents one of the buckling beams of the cluster from making electrical contact with the feature to be tested, the other one or more of the buckling beams of the cluster will make the required electrical connection.

Abstract: A multi-layer ceramic capacitor and method of manufacturing the capacitor, the capacitor having signal vias surrounded by an area containing a material having a low dielectric constant, the via and surrounding area of low dielectric constant material inserted in a material having a high dielectric constant.

Abstract: A power booster and current measuring circuit provides a quiet, accurate voltage to a load (such as a transistor during parametric testing) with a load current of up to 1 ampere, and can measure that load current to an accuracy of ±0.1 % over a range of currents extending nine orders of magnitude (e.g., 1 ampere to 10−9 amperes). The load voltage is supplied by a sense driver, a bypass driver, or both. The bypass driver comprises a high-current operational amplifier with a direct feedback loop (e.g., a voltage follower). The sense driver comprises a high-impedance operational amplifier having a feedback loop comprising a high-current operational amplifier connected as a voltage follower and one of a series of sense resistors having different values.

Abstract: The invention provides a PIN diode having a laterally extended I-region. The invention also provides a method of fabricating the inventive PIN diode compatible with modern RF technologies such as silicon-germanium BiCMOS processes.

Abstract: A jig for aligning a wafer-handling system in a calibration location, such as a wafer pickup-dismount location, with respect to a wafer-processing tool. The jig comprises an alignment fixture adapted to be repeatably mounted on the tool and having one or more edge stops. The jig may further comprise an edge-to-center locator adapted to be mounted on the alignment fixture. The edge-to-center locator has a peripheral edge and a center marker that identifies the precise center of the calibration location when the edge-to-center locator edge is positioned in contact with the edge stop or stops. An alignment method for use of the jig is also disclosed.

Abstract: A method for optically measuring lithographic process bias of a minimum feature formed by a lithographic process. The method comprises creating on a substrate an array of elements from which a darkfield optical image is generated and detected, electronic information corresponding to the image is generated and processed, and the difference between the created length versus the nominal length of the elements is calculated to determine lithographic process bias. The darkfield optical image may be a double-lobe optical image, and signal processing may comprise creating a normalized intensity profile to overcome film-thickness dependencies, to which one or more noise-rejecting, edge-detection methods is or are applied to calculate the created length of the elements. A method for using double-lobe darkfield imaging for general edge detection is also disclosed.

Abstract: A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced.