Patents Represented by Attorney, Agent or Law Firm Tom Chen
  • Patent number: 6821035
    Abstract: An impact printer with a hammerbank having print hammers retained by a permanent magnet for impacting a print ribbon, and a mechanical driver for moving the hammerbank across print media. First and second coils for each hammer are wrapped around first and second pole pieces, one of which is asymmetrical to the other pole piece. One of the pole pieces can have a generally elongated longitudinal form with the coil wound around the longitudinal form and the other can have a generally arcuate form, with the coil wrapped on a portion between the ends thereof. The coil wrapped around the arcuately formed pole piece is thicker than the coil wrapped around the longitudinal pole piece. The result is to provide pole pieces and coils for an impact printer having differing spatial relationships that can be staggered, or formed asymmetrically for more compact coil and pole piece placement to improve printer efficiency.
    Type: Grant
    Filed: April 10, 2002
    Date of Patent: November 23, 2004
    Assignee: Printronix, Inc.
    Inventor: John W. Gemmell
  • Patent number: 6794290
    Abstract: A method is provided for filling high aspect ratio gaps without void formation by using a high density plasma (HDP) deposition process with a sequence of deposition and hydrogen etch steps. The first step uses an etch/dep ratio less than one to quickly fill the gap. The first step is interrupted before the opening to the gap is closed. The second step uses a hydrogen-based plasma to chemically etch the deposited material to widen the gap. The second step is stopped before corners of the elements forming the gaps are exposed. These steps can be repeated until the aspect ratio of the gap is reduced so that void-free gap-fill is possible. The etch/dep ratio and duration of each step can be optimized for high throughput and high aspect ratio gap-fill capacity.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: September 21, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: George D. Papasouliotis, Robert D. Tas
  • Patent number: 6790773
    Abstract: A process and structure are provided that allows electroplating to fill sub-micron, high aspect ratio features using a non-conformal conductive layer between the dielectric layer and the platability layer. The conductive layer is a relatively thick layer overlying the planar surface of the wafer and the bottom of the features to be filled. Little or no material of the conductive layer is formed on the feature sidewalls. The thick conductive layer on the field provides adequate conductivity for uniform electroplating, while the absence of significant conductive material on the sidewalls decreases the aspect ratio of the feature and makes void-free filling easier to accomplish with electroplating. Further, the absence of significant material on the sidewalls allows a thicker barrier layer to be formed for higher reliability.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: September 14, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: John S. Drewery, Ronald A. Powell
  • Patent number: 6779935
    Abstract: An impact line printer comprising a print ribbon wound on a pair of spools for traversal in two directions across a plurality of print hammers having tips for impacting the print ribbon to print on a media. A permanent magnet having two pole pieces having pole piece ends in adjacent relationship to the print hammers retains the print hammers until a coil in associated relationship with each pole piece releases the magnetic retention of the hammers. A magnetically permeable extension is longitudinally adjacent each hammer which acts as a magnetic shunt to permit more rapid printing rates and higher impacts. The extensions conduct and shunt magnetic flux from the hammers through the longitudinally adjacent extensions.
    Type: Grant
    Filed: February 6, 2003
    Date of Patent: August 24, 2004
    Assignee: Printronix, Inc.
    Inventor: John W. Gemmell
  • Patent number: 6774039
    Abstract: Copper bus bars are formed between adjacent die on a wafer during the process flow. The bus bars are between 50 and 100 &mgr;m wide and between 2 and 5 &mgr;m deep. A barrier layer is formed between the bus bars and the die to prevent copper diffusion. A dielectric layer is deposited over the bus bars and die and etched with contacts and features, such as vias. A seed layer is subsequently deposited over the wafer, which allows electrical conductance between the bus bars and the die during a subsequent electroplating process to fill the features and contacts. The bus bars carry electroplating current from the die edge to the die center. As a result, current does not need to be carried by a low sheet resistivity seed layer from the wafer edge to the center. This allows the seed layer to be thinner and of materials other than copper. Further, thinner seed layers allow thicker barrier layer for more reliability.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: August 10, 2004
    Assignee: Novellus Systems, Inc.
    Inventor: John S. Drewery
  • Patent number: 6403501
    Abstract: A method is provided that conditions the chamber walls of a HDP CVD reactor by forming a layer of doped material prior to depositing dielectric layers of the doped material onto wafers. A consistent deposition rate can be maintained during subsequent deposition. When deposition is halted, the chamber is cleaned and a thin layer of the doped material is formed on the walls. Consequently, the chamber is kept at equilibrium even during periods of idle, thereby allowing the deposition rates to be consistent even after deposition resumes after the idle periods. For prolonged idle times, the chamber is re-cleaned and the doped material is re-deposited periodically, such as every 12 hours.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: June 11, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: Jonathan W. Hander, Mahesh K. Sanganeria, Julian J. Hsieh
  • Patent number: 6405101
    Abstract: Disclosed is a system and method for detecting the position of a wafer with respect to a calibrated reference position. In one embodiment of the invention, sensors are used to detect the edges of the wafer as the wafer is being passed over the sensors. This wafer detection information is then used to calculate the amount by which the wafer is off-centered such that corrections can be made before the wafer is placed onto a destination location.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: June 11, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: William R. Johanson, Craig Stevens, Steve Kleinke, Damon Genetti
  • Patent number: 6395150
    Abstract: A process for filling high aspect ratio gaps on substrates uses conventional high density plasma deposition processes, with an efficient sputtering inert gas, such as Ar, replaced or reduced with an He inefficient sputtering inert gas such as He. By reducing the sputtering component, sidewall deposition from the sputtered material is reduced. Consequently, gaps with aspect ratios of 6.0:1 and higher can be filled without the formation of voids and without damaging circuit elements.
    Type: Grant
    Filed: April 1, 1998
    Date of Patent: May 28, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: Patrick A. Van Cleemput, George D. Papasouliotis, Mark A. Logan, Bart van Schravendijk, William J. King
  • Patent number: 6348742
    Abstract: A bond pad structure is provided which has a primary bond pad region electrically connected to a secondary bond pad region. The secondary bond pad region is used to test a circuit for configuration, while the primary bond pad is covered with a protective oxide. After configuration and etching to complete desired disconnections, the oxide is removed from the primary bond pad region, leaving an undamaged surface for subsequent wire bonding. The primary bond pad region and the secondary bond pad region can be a unitary structure or two separate structures.
    Type: Grant
    Filed: January 25, 1999
    Date of Patent: February 19, 2002
    Assignee: Clear Logic, Inc.
    Inventor: John MacPherson
  • Patent number: 6349092
    Abstract: The present invention provides a method and structure for allowing more than 16 nodes to be configured in a single SONET BLSR network by utilizing unused portions of the transport overhead of an STS-N frame to expand the node identification field from 4 bits to 8 bits, thereby allowing up to 256 nodes to be present on a single ring.
    Type: Grant
    Filed: November 16, 1998
    Date of Patent: February 19, 2002
    Assignee: Cisco Systems, Inc.
    Inventors: Patrick R. Bisson, Paul M. Elliott, Kate B. Amon, Anurag Nigam, Phu S. Le
  • Patent number: 6346748
    Abstract: A method for patterning a layer of photoresist includes the steps of 1) exposing the photoresist through a standard precision mask to define all possible cut points, 2) etching all possible cut points in a dielectric layer, 3) selectively exposing a second layer of photoresist with a non-precision targeting energy beam or mask to select the desired cut points. Consequently, no custom precision masks are required to pattern the various layers of photoresist during the fabrication of application specific integrated circuits (ASICs), thereby reducing both the lead-time and costs for manufacturing ASICs.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: February 12, 2002
    Assignee: Clear Logic, Inc.
    Inventor: Alan H. Huggins
  • Patent number: 6340628
    Abstract: A chemical vapor deposition (CVD) process uses a precursor gas, such as with a siloxane or alkylsilane, and a carbon-dioxide-containing gas, such as CO2 with O2 or CO2 with CxH(2x+1)OH where 1≦x≦5, to deposit a dielectric layer with no photoresist “footing”, a low dielectric constant, and high degrees of adhesion and hardness. Because nitrogen is not used in the deposition process (the carbon-dioxide-containing gas replaces nitrogen-containing gases in conventional processes), amines do not build into the deposited layer, thereby preventing photoresist “footing”.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: January 22, 2002
    Assignee: Novellus Systems, Inc.
    Inventors: Patrick A. Van Cleemput, Ravi Kumar Laxman, Jen Shu, Michelle T. Schulberg, Bunsen Nie
  • Patent number: 6321765
    Abstract: A mass flow controller has a sensor section that generates an electrical signal, dependent on the measured flow rate. The controller sends a control signal to a magnetic field generating unit, dependent upon the actual flow rate and the desired flow rate, which in response, generates a magnetic flux in the direction of the fluid input to the fluid output through the body of the controller. This means that the magnetic flux is concurrent with the fluid flow within the mass flow controller body. The magnetic flux alters the position of a plunger button assembly, located between the bypass chamber and the fluid output, relative to an orifice plate to control the flow rate to obtain the desired output flow. By incorporating the proportional control valve within the mass flow controller body, the need for a separate and large valve section is eliminated, reducing the size and cost of the controller.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: November 27, 2001
    Inventor: Rajinder S. Gill
  • Patent number: 6324322
    Abstract: A fused-fiber multi-window wavelength filter (MWF) is constructed with an unbalanced Michelson Interferometer, in which input light passing through the fused coupling region is decoupled and travels along two fibers of different optical path lengths. The two light signals travel to the end of the two fibers, where a highly reflective coating reflects the light back toward the coupling region, where the signals are coupled again and then decoupled after exiting the coupling region. By adjusting the optical path length difference, either by changing the length or refractive index, a signal at a desired wavelength can be obtained at the filter output. The MWF can be combined with other MWFs to form more compact sized multi-window wavelength division multiplexers (MWDMs) and dense WDMs. Passive thermal compensation techniques can be applied to one or both of the reflecting fibers to maintain the desired optical path length difference.
    Type: Grant
    Filed: June 7, 1999
    Date of Patent: November 27, 2001
    Assignee: WaveSplitter Technologies, Inc.
    Inventors: Huali Luo, Chi-Hung Huang, Joseph C. Chon
  • Patent number: 6288937
    Abstract: A method and system are provided which allows N programmable cells to be used to select one of 2N signals for routing to a desired destination, such as a programmable array logic (PAL), for further processing. N input selection signals are used to generate N selection signals and their corresponding complements using N programmable cells. These selection signals are then used to generate coded selection signals, which can be separated into groups of one or more. Each group of coded selection signals is then decoded, such as with K×1 tree decoders, where K is not greater than 2N. Tree decoders are typically cascaded such that the first stage or group of decoders select a portion of the 2N signals and then subsequent decoder(s) select portion(s) of the previous selected signals until the one desired signal is selected from the 2N signals. A different set of N input selection signals can be used to select a signal from the same 2N signals in order to select more than one of the 2N signals.
    Type: Grant
    Filed: May 10, 2000
    Date of Patent: September 11, 2001
    Assignee: Lattice Semiconductor Corporation
    Inventor: Loren McLaury
  • Patent number: 6263128
    Abstract: According to the present invention, a multi-window wavelength division multiplexer (MWDM) is coupled to a correcting filter characterized by a shallow modulation depth and a channel separation smaller than the MWDM. A correcting filter is coupled to an input of the MWDM or to each of the two outputs of the MWDM. By changing the modulation depth and/or channel separation of the correcting filter(s), the spectral response of the filter can be adjusted to produce a more uniform gain (i.e., a “flat-top” spectral response) across wavelengths of passbands within the MWDM. In one embodiment, the correcting filter is an unbalanced Mach-Zehnder interferometer formed with two fused-fiber couplers having non-equal splitting ratios. In other embodiments, the correcting filter is a Fabry-Perot interferometer having a low end-face reflectivity.
    Type: Grant
    Filed: June 2, 1999
    Date of Patent: July 17, 2001
    Assignee: WaveSplitter Technologies, Inc.
    Inventor: Chi-Hung Huang
  • Patent number: 6256433
    Abstract: An optical add/drop filter (OADF) module is provided that is capable of only utilizing one filter to drop and add multiple channels from a multiplexed signal. In one embodiment, a demultiplexer separates the input signal into groups of signals or channels to be dropped. This group of channels is coupled to one input of a 2×2 interleaving OADF, which in one embodiment is an unbalanced Mach-Zehnder Interferometer, while another group of channels to be added back to the multiplexed signal is coupled to the other input. One output of the OADF drops one group of channels, while the other output transmits the added group of channels to an input of a multiplexer, which combines the group of added channels with the other groups of channels from the outputs of the demultiplexer. In another embodiment, a multi-window filter formed from an unbalanced Michelson Interferometer outputs two signals, each having either odd or even wavelength signal components.
    Type: Grant
    Filed: September 24, 1999
    Date of Patent: July 3, 2001
    Assignee: Wavesplitter Technologies, Inc.
    Inventors: Huali Luo, Joseph C. Chon, Jerry R. Bautista, Sheau-Sheng Chen
  • Patent number: 6239480
    Abstract: A structure and method are provided to allow a die to be packaged more uniformly and in parallel with a package by utilizing a lead frame having at least one cavity within the lead frame, thereby allowing excess die-attach epoxy can flow into the cavity or cavities and reducing the amount of contact surface area between the die and lead frame.
    Type: Grant
    Filed: July 6, 1998
    Date of Patent: May 29, 2001
    Assignee: Clear Logic, Inc.
    Inventors: John MacPherson, Wendy Eng
  • Patent number: 6235556
    Abstract: A structure and method are provided to allow a die to be packaged more uniformly and in parallel with a package by utilizing a lead frame having at least one cavity within the lead frame, thereby allowing excess die-attach epoxy can flow into the cavity or cavities and reducing the amount of contact surface area between the die and lead frame.
    Type: Grant
    Filed: September 4, 1998
    Date of Patent: May 22, 2001
    Assignee: Clear Logic, Inc.
    Inventors: John MacPherson, Wendy Eng
  • Patent number: 6228564
    Abstract: A method for patterning a layer of photoresist includes the steps of 1) exposing the photoresist through a standard precision mask to define all possible patterns and features, and 2) selecting desired patterns and features with a non-precision targeting energy beam or mask. Consequently, no custom precision masks are required to pattern the various layers of photoresist during the fabrication of application specific integrated circuits (ASICs), thereby reducing both the lead-time and costs for manufacturing ASICs.
    Type: Grant
    Filed: August 18, 1999
    Date of Patent: May 8, 2001
    Assignee: Clear Logic
    Inventor: Alan H. Huggins