Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A select transistor can have a source which also acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor operates as a charge injector. The charge injector provides electrons for substrate hot electron injection of electrons onto the floating gate for programming. The cell depletion/inversion region may be extended by forming a capacitor as an extension of the control gate over the substrate between the source and channel of said sense transistor.

Abstract: A chassis which comprises a first frame and a second frame is provided. The first frame includes a front surface and a pair of first flanges formed on opposing edges of the front surface. The second frame includes a pair of side surfaces. Each side surface has an edge with a second flange and a plurality of aligned guide elements. The second flanges and the guide elements define guide channels for slidably receiving the first flanges. A cover assembly for the chassis comprises a panel having a first inner surface, a hook, and a standoff projecting from the first inner surface. The hook has a leg portion and an arm portion which may be inserted into a slot in one of the surfaces of the chassis.

Abstract: The invention, in one embodiment, is a method for stacking receptacles. The method comprises stacking a first receptacle on a second receptacle; and inverting the stacked first and second receptacles to engage the first and second receptacles.

Abstract: A system includes memory banks and a circuit. The memory banks store data that is indicative of a pixel image, and the image includes lines of pixels. For each pair of adjacent lines, the circuit stores a first subset of the data (that is indicative of one line of the pair) in one of the memory banks and stores a second subset of the data (that is indicative of the other line of the pair) in another of the memory banks.

Abstract: The invention discloses apparatus and process in which data files are distributed across a large scale data processing system to enable balance of work loads and storage loads at a plurality of nodes. Specifically, the invention provides significant advances in data base management by distributing meta-data in a plurality of file storage nodes to isolatively and distributively store file data in a distributed computing environment. This provides efficient allocation of storage space and work loads among nodes.

Abstract: Semiconductor devices may be made by forming a silicided layer on a silicon material such as that used to form the extractor of a field emission display. The silicided layer may be self-aligned with the emitter of a field emission display. If the silicided layer is treated at a temperature above 1000.degree. C. by exposure to a nitrogen source, the silicide is resistant to subsequent chemical attack such as that involved in a buffered oxide etching process.

Abstract: A nonvolatile memory cell which is highly scalable includes a cell formed in a triple well. A pair of sources for a pair of cells on adjacent word lines each acts as the emitter of a lateral bipolar transistor. The lateral bipolar transistor of one cell operates as a charge injector for the other cell. The charge injector provides carriers for substrate hot carrier injection onto a floating gate.

Abstract: A chassis which comprises a first frame and a second frame is provided. The first frame includes a front surface and a pair of first flanges formed on opposing edges of the front surface. The second frame includes a pair of side surfaces. Each side surface has an edge with a second flange and a plurality of aligned guide elements. The second flanges and the guide elements define guide channels for slidably receiving the first flanges. A cover assembly for the chassis comprises a panel having a first inner surface, a hook, and a standoff projecting from the first inner surface. The hook has a leg portion and an arm portion which may be inserted into a slot in one of the surfaces of the chassis.

Abstract: A quartz tank for wet semiconductor wafer processing includes one or more ports extending through the tank for the exchange of fluids with the tank. The openings may be aligned with a T-shaped quartz stem having an enlarged end retained on the interior side of said quartz tank in sealing abutment therewith. The lower end of the quartz stem may have external threads to abut with a suitable union. The union may include a nut having a reduced diameter lower end to engage an enlarged end of the tubing member connected to the bottom of the quartz stem. An o-ring seal may be sandwiched between the tubing and the lower end of the quartz stem. The nut may be formed of a carbon-fiber reinforced fluorocarbon material such as perfluoroalkoxy.

Abstract: A recorder with a global positioning system receiver may record video frames and/or audio data in association with global positioning system coordinates. In this way, the user may readily determine the location of associated photographs taken digitally and may recreate excursions using a multimedia approach. Using mapping software, the digital images may be associated with map locations as well, so that the user may select given map locations to view associated video. By making the device of a portable size, the user may take the device on excursions and may receive information about various points which are associated on a digital map including both audio and video. At the same time, the user can create multimedia presentations about a variety of locations as the user goes from point to point.

Abstract: A computer system includes a desk top computer and a portable computer. The desktop computer can be operatively connected to the portable computer and can perform symmetrical processing.

Abstract: The invention, in one embodiment, is a receptacle including a body having a first and second surfaces and a pin. The first surface includes a first opening from a first slot in the body, the first slot being obliquely disposed relative to the first surface. The second surface includes a second opening from a second slot in the body, the second slot being obliquely disposed relative the second surface in parallel relation to the first slot, the first and second openings being vertically aligned The pin is reciprocable within the second slot.

Abstract: The invention, in one embodiment is a cable management device. The device includes an elongated tray having a first surface and a second surface. The first surface further comprises a notched section continuous with the first surface; and a first end on the notched section distal from the first surface. The second surface further is continuous with the first surface and angularly disposed relative thereto and has a second end. The device also includes a cover attachable to the first end and to the second end.

Abstract: Solder paste is deposited using a solder stencil with an aperture having a concave edge in order to reduce the formation of solder balls. The solder deposit may be formed on a pad such that the paste has a concave edge. Solder paste deposits may be made on adjacent pads with the concave surfaces facing one another.

Abstract: The invention, in one embodiment, is method for managing solutions to problems. The method includes accessing a first store containing at least one issue and at least one pre-existing solution associated with the issue; and importing the first store into a second store, the second store being remote from the first store.

Abstract: A semiconductor assembly includes two leads, a primary die and a secondary support structure. Impedance networks of the secondary support structure establish an impedance between each lead and a different bond pad of the primary die. Although the distances between each bond pad and lead are substantially different, the impedances between each bond pad and lead are substantially the same.

Abstract: A high-throughput memory access interface allows higher data transfer rates between a system memory controller and video/graphics adapters than is possible using standard local bus architectures. The interface enables data to be written directly to a peripheral device at either one of two selectable speeds. The peripheral device may be a graphics adapter. A signal indicative of whether the adapter's write buffers are full is used to determine whether a write transaction to the adapter can proceed. If the transaction can not proceed at that time, it can be enqueued in the interface.

Abstract: A memory device provides for multi-way set associative burst SRAM (static random access memory) cache memory in a single device or package. In one embodiment input address bit A2 is used to generate a bank select signal rather than as a direct input to the SRAM's memory array element. This, in combination with additional output registers and output buffers creates a two-way set associative cache memory in a single memory device. In an alternative embodiment, input address bits A2 and A3 are used to generate bank select signals rather than as direct input to the SRAM's memory array element. This, in combination with additional output registers, output buffers, and an output bank decoder creates a four-way set associative cache memory in a single memory device. Additionally, a mode circuit is provided that controls whether the memory device operates as a multi-way set associative memory or as a conventional direct-mapped memory device.

Abstract: Apparatus and method of increasing the distance of the gap between a lead frame and a semiconductor die surface in a package assembly. An adhesive layer and a gap increasing layer are disposed between the lead frame and the semiconductor die surface. The gap increasing layer has a thickness selected to reduce likelihood of package particles from being trapped between the lead frame and the die surface. The gap increasing layer includes silver plating, and has a thickness of at least about 300 to 500 microinches.

Abstract: An integrated circuit has circuitry formed by a fabrication process. The circuitry has an electrical characteristic that is different from a predetermined value due to variations in the fabrication process. The electrical characteristic is responsive to a level of a current, and a current source of the integrated circuit is configured to be selectably enabled to adjust the level of the current to move the electrical characteristic closer to the predetermined value.