Abstract: A process is provided for creating microstructure coupling guides for aligning photonic devices with optical signal carrying apparatuses. The process includes applying a photoresist to a semiconductor material, spinning the semiconductor material, baking the semiconductor material, exposing the photoresist, baking the semiconductor material a second time, and developing the resist. The process creates a microstructure that acts as an integral guide to align and maintain the relative position between an optical signal carrying apparatus and a photonic device.

Abstract: A process for use in fabrication of a semiconductor device is disclosed. The fabricated semiconductor device includes a top oxide aperture within a top oxidation layer and a bottom oxide aperture within a bottom oxidation layer precisely positioned relative to each other, and an electrical contact to a contact layer between the top and bottom oxidation layers. The process includes the following steps: etching past one of the oxidation layers and stopping in the contact layer, etching one or more holes traversing the top and bottom oxidation layers, and simultaneously oxidizing both oxidation layers. Etching past both oxidation layers in the same alignment step ensures that the centers of the two apertures, as formed through selective oxidation, will be aligned.

Abstract: A package for mounting an integrated circuit chip includes a body having at least a first region, the size of the integrated circuit chip, and a second region. The first region has a first coefficient of thermal expansion (CTE), and the second region has a second, different CTE. The first region approximately matches the CTE of the integrated circuit chip mounted on the package, and the second region approximates the CTE of the printed wiring board to which the package is mounted.

Abstract: A method for forming a through-via in a laminated substrate by laser drilling the through-via in a laminated substrate from a top exposed surface of the substrate to a bottom exposed surface of the substrate using a plurality of laser pulses that are trepanned in a first predetermined pattern. Each pulse trepanned in the first predetermined pattern has a first energy density per pulse. Then, the through-via is laser drilled using a plurality of laser pulses that are trepanned in a second predetermined pattern. Each pulse trepanned in the second predetermined pattern has a second energy density per pulse that is greater than the first energy density per pulse. The second predetermined pattern is within the first predetermined pattern.

Abstract: The present invention relates to assembly techniques and the resulting products which are thermally stable, have high structural integrity, and compensate for thermal stresses that occur between the various components of the package. This is accomplished, in-part, by designing the package so that the coefficient of thermal expansion (CTE) of a stiffening ring which is mounted on the package substrate matches the CTE of the substrate and optional lid. Further, the particular adhesives used to bond the stiffening ring are chosen to match their CTE to that of the substrate, ring and lid. Moreover, the substrate is designed so that its CTE, at least in-part, matches that of the chip, and also that of the stiffening ring.

Abstract: A constraining ring increases the modulus of an interconnect substrate to maintain flatness of the substrate. The constraining ring is made of materials selected to match the coefficient of thermal expansion of the substrate to that of the constraining ring. Circuit components including capacitors and resistors are formed on the constraining ring to provide enhanced electrical properties without adding to the size of the device.

Abstract: A process is provided for creating microstructure coupling guides for aligning photonic devices with optical signal carrying apparatuses. The process includes applying a photoresist to a semiconductor material, spinning the semiconductor material, baking the semiconductor material, exposing the photoresist, baking the semiconductor material a second time, and developing the resist. The process creates a microstructure that acts as an integral guide to align and maintain the relative position between an optical signal carrying apparatus and a photonic device.

Abstract: An electronic chip package is provided having a laminated substrate. The laminated substrate includes at least one conductive layer and at least one dielectric layer which is bonded to the conductive layer. The dielectric layer has a glass transition temperature T.sub.g greater than 200.degree. C. and a volumetric coefficient of thermal expansion of .ltoreq.75 ppm/.degree.C. A semiconductor device is electrically attached to the laminated substrate.

Abstract: A method for forming a through-via in a laminated substrate by laser drilling the through-via in a laminated substrate from a top exposed surface of the substrate to a bottom exposed surface of the substrate using a plurality of laser pulses that are trepanned in a first predetermined pattern. Each pulse trepanned in the first predetermined pattern has a first energy density per pulse. Then, the through-via is laser drilled using a plurality of laser pulses that are trepanned in a second predetermined pattern. Each pulse trepanned in the second predetermined pattern has a second energy density per pulse that is greater than the first energy density per pulse. The second predetermined pattern is within the first predetermined pattern.

Abstract: A method of making a laminated substrate by forming a registration mark on a core layer of the substrate. Then, forming a first layer on the core layer using the registration mark as a fiducial registration point. The first layer is laser drilled through to expose the registration mark on the core layer. A second layer is then formed on the first layer using the registration mark as a fiducial point.

Abstract: A method of manufacturing a multi-layered structure includes forming first and second layers, patterning the first layer, determining a distribution of material in at least one area of the first layer, and altering the material content of one of the first and second layers in at least one of the first layer area and a corresponding area of the second layer to approximately match the material content of the first layer and second layers.

Abstract: A compact WDM optical device can demultiplex an optical laser signal containing several different wavelengths corresponding to particular channels, and, in reverse operation operate as a multiplexer to interleave several different wavelengths into a multiplexed multi-channel optical laser signal with improved insertion loss characteristics. The optical device includes a linear array of passive resonant optical cavities, in the form of Fabry-Perot filters, extending in a lateral direction and an integral array of associated microlenses extending in the lateral direction. Each microlens has a center which is offset from the central longitudinal axis of an associated Fabry-Perot filter to reflect laser radiation through the device. Each optical cavity is tuned by adjusting the longitudinal dimension thereof to a particular wavelength contained in the multi-channel optical signal. A stepped-wavelength steered laser radiation source for the optical device uses a VCSEL array with offset microlenses.

Abstract: A method for forming a through-via in a laminated substrate by laser drilling the through-via in a laminated substrate from a top exposed surface of the substrate to a bottom exposed surface of the substrate using a plurality of laser pulses that are trepanned in a first predetermined pattern. Each pulse trepanned in the first predetermined pattern has a first energy density per pulse. Then, the through-via is laser drilled using a plurality of laser pulses that are trepanned in a second predetermined pattern. Each pulse trepanned in the second predetermined pattern has a second energy density per pulse that is greater than the first energy density per pulse. The second predetermined pattern is within the first predetermined pattern.

Abstract: A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed.

Abstract: A low dielectric constant material is provided for use as an insulation element in an electronic device, such as but not limited to an integrated circuit structure for example. Such a low dielectric constant material may be formed from an aqueous fluoropolymer microemulsion or microdispersion. The low dielectric constant material may be made porous, further lowering its dielectric constant. The low dielectric constant material may be deposited by a spin-coating process and patterned using reactive ion etching or other suitable techniques.

Abstract: The present invention relates to a system and method for performing reliability screening on semi-conductor wafers and particularly to a highly planar burn in apparatus and method for uses including wafer level burn-in (WLBI), diced die burn-in (DDBI), and packaged die burn-in (PDBI). The burn-in system includes a burn-in substrate with a planar base, a temporary Z-axis connecting member, and a Z-axis wafer level contact sheet electrically coupled to one another for screening wafers, diced die, and packaged electronic components, their assembly and use.

Abstract: A method of minimizing warp and die stress in the production of an electronic assembly includes connecting one surface of a die to a package, and connecting an opposite surface of the die to a lid disposed over a constraining ring that is mounted to the package. The lid has a size, shape and coefficient of thermal expansion (CTE) selected to generate a bending moment that opposes bending moments resulting from connecting the die to the package.

Abstract: A method of forming a through-via in a laminated substrate by applying a polymeric photo-absorptive layer on an exposed bottom surface of a laminated substrate. A through-via is laser drilled in the substrate from a top of the substrate through the substrate to a bottom of the substrate. The photo-absorptive layer formed on the bottom surface of the substrate is then removed.

Abstract: A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

Abstract: A semiconductor flip chip package is provided having a semiconductor flip chip integrated circuit device and a laminated substrate. The laminated substrate has a conductive core and at least one lamina formed on the core layer. Each lamina has a dielectric layer and a conductive layer. The dielectric layer is formed at least in part from a fluoropolymer material having disposed therein an inorganic filler material. At least one via extends through the at least one lamina. The via has an entrance aperature of <75 microns and an aspect ratio of between 3:1 and 25;1. The laminated substrate includes a plurality of individual pads to which the individual solder ball connections of the semiconductor flip chip integrated circuit device are connected.