Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.

Abstract: The technology is a system and method for selecting a television lineup. The available television lineups capable of being viewed on a digital device are identified. One of the tuner positions is selected and the television channel designated in each available television lineup identified. If any of the television channels identified is a likely identifiable channel and is designated by approximately half of the available television lineups, available television lineups may be deleted based on the television signal received by the selected tuner position. In on embodiment, the tuner positions are selected in numerical order. In an alternative embodiment, the tuner positions are first sorted before one is selected. It may not be possible to delete lineups based on likely identifiable channels. In this case, a viewer may be prompted to identify a channel.

Abstract: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level.

Abstract: A handheld electronic device for use at a venue hosting a live sporting event, having a receiver for receiving a wireless RF transmission conveying a plurality of video streams derived from video cameras filming the live sporting event, a display and a user interface for selecting a video stream among the plurality of video streams to be displayed on the display. The handheld electronic device is capable to acquire a locked mode of operation and an unlocked mode of operation, in the locked mode of operation the handheld electronic device being precluded from displaying the video streams to a spectator, in the unlocked mode of operation the handheld electronic device being enabled to display the video streams to the spectator, the handheld electronic device capable to acquire the unlocked mode of operation in response to reception of authentication data wirelessly transmitted to the handheld electronic device.

Abstract: A handheld electronic device for use at a venue hosting a live sporting event, having a receiver for receiving a wireless RF transmission conveying a plurality of video streams derived from video cameras filming the live sporting event, a display and a user interface for selecting a video stream among the plurality of video streams to be displayed on the display. The handheld electronic device is capable to acquire a locked mode of operation and an unlocked mode of operation, in the locked mode of operation the handheld electronic device being precluded from displaying the video streams to a spectator, in the unlocked mode of operation the handheld electronic device being enabled to display the video streams to the spectator, the handheld electronic device capable to acquire the unlocked mode of operation in response to reception of authentication data wirelessly transmitted to the handheld electronic device.

Abstract: A peripheral device is disclosed having two associated memory modules, and which is configured to fit within the ExpressCard slot. One memory module communicates with a host over the PCIe bus interface of the ExpressCard slot, while the other memory module communicates with the host over the USB interface of the ExpressCard slot.

Abstract: Authenticating the source of digital media is performed by using unique, randomly generated variably encoded frequency patterns to create mastering specific, profiles for sets end user media which can be verified by a manufacturer. A method for verifying the authenticity of an optical storage device includes the steps of: reading a randomly generated signature key value for the optical storage device; determining manufacturing information for the optical storage device; and matching read randomly generated signature key values and manufacturing information with known valid key the to determine the authenticity of the device.

Abstract: In one aspect, an image of an event is obtained from a camera, and an object is detected in the image. Data of a textured 3d model of the event and data from the object are combined to depict virtual viewpoints of the event which differ from a real viewpoint of the camera. The object is at least partially faded out at a virtual viewpoint which meets a specified criterion, such as a specified angular offset, or exceeding a specified difference from the viewpoint of the camera. The fading can occur over multiple virtual viewpoints, or over a time period in which the fading is otherwise apparent to a human viewer. In another aspect, an animation is provided in which one object is faded out at a specified virtual viewpoint so that it does not fully occlude another object. For instance, the objects can be participants in a sports event.

Abstract: Optimized verify and read pass voltages are obtained to improve read accuracy in a non-volatile storage device. The optimized voltages account for changes in unselected storage element resistance when the storage elements become programmed. This change in resistance is referred to as a front pattern effect. In one approach, the verify pass voltage is higher than the read pass voltage, and a common verify voltage is applied on the source and drain sides of a selected word line. In other approaches, different verify pass voltages are applied on the source and drain sides of the selected word line. An optimization process can include determining a metric for different sets of verify and read pass voltages. The metric can indicate threshold voltage width, read errors or a decoding time or number of iterations of an ECC decoding engine.

Abstract: A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.

Abstract: Synthetic transactions for a network system are generated based on monitoring of the network system. One or more network system monitoring systems receive network system traffic, traffic monitoring data and/or application runtime data during a monitoring process. The traffic monitoring data may be derived from network system traffic and the application runtime data may be data associated with application transactions. The traffic, traffic monitoring data and application runtime data may contain information regarding the scope and frequency of the functionality tested by the actual traffic received by the network system. Synthetic transactions may be generated and transmitted to test the network system based on the scope and frequency of the functionality tested by actual traffic.

Abstract: Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming process and performing one or more sensing operations at one or more alternative results for the non-volatile storage elements. Subsequent programming process are adjusted based on a first alternative result and the identification of the program pulse if the one or more sensing operations determined that greater than a predetermined number of non-volatile storage elements achieved the first alternative result.

Abstract: A subject's heart rate is determined. A heart rate monitor receives a Doppler signal reflected from an artery of a target, performs demodulation and heart beat recognition techniques to determine a set of features in each frame of the signal. Pattern classification is performed to determine if the extracted feature sequence is associated with heart beats. The pattern classification may include finding the optimal state sequence by calculating the probability of each allowable state sequence based on the extracted feature sequence and heart beat models or additional noise models. Or, a heart beat candidate is determined using frame energy and dynamic thresholding followed by computing the probabilities between the feature sequence and each stored heart beat model or additional noise models. Or, heart beat candidates are determined using frame energy and dynamic thresholding which compute the similarity between the feature sequences and each of the stored heart beat templates.

Abstract: Program disturb is reduced in a non-volatile storage system during a programming operation by switching from using programming pulses of a longer duration to programming pulses of a shorter duration, partway through the programming operation. A switchover point can be based on temperature, selected word line position and/or tracking of storage elements to a trigger state. The switchover point occurs sooner for higher temperatures, and for drain side word lines. The trigger state can be selected based on temperature. A portion of storage elements which are required to reach the trigger state to trigger a switchover can also be set a function of temperature. Programming pulses of a shorter duration improve channel boosting for inhibited storage elements, thereby reducing program disturb for these storage elements.

Abstract: A charge pump with a MOS-type capacitor, where the MOS-type capacitor is operated in an inversion region in which capacitance varies as a function of the frequency of the applied signal. The charge pump is switched to transfer charge from an input node to the capacitor and from the capacitor to an output node. During a transition interval, a relatively high frequency switching signal is used to lower the capacitance and increase efficiency. During a settling interval, a relatively low frequency switching signal is used, in which case the capacitance is higher, but similar to a level which would be seen if the capacitor was operated in an accumulation region. MOS capacitor dimensions and switching intervals are mutually optimized to provide high efficiency and required throughput. The charge pump may be configured as a voltage multiplier, divider, inverter or follower, for instance.

Abstract: An integrated circuit device having a selectable data rate clock data recovery (CDR) circuit and a selectable data rate transmit circuit. The CDR circuit includes a receive circuit to capture a plurality of samples of an input signal during a cycle of a first clock signal. A select circuit is coupled to the receive circuit to select, according to a receive data rate select signal, one of the plurality of samples to be a first selected sample of the input signal and another of the plurality of samples to be a second selected sample of the input signal. A phase control circuit is coupled to receive the first and second selected samples of the input signal and includes circuitry to compare the selected samples to determine whether the first clock signal leads or lags a transition of the input signal. The transmit circuit includes a serializing circuit to receive a parallel set of bits and to output the set of bits in sequence to an output driver in response to a first clock signal.

Abstract: A technique for performing read operations with reduced errors in a memory device such as flash memory. An automatic gain control approach is used in which cells which have experienced data retention loss are read by a fine M-level quantizer which uses M-1 read threshold voltage levels. In one approach, M-quantized threshold voltage values are multiplied by a gain to obtain gain-adjusted threshold voltage values, which are quantized by an L-level quantizer, where L<M, by comparing the gain-adjusted threshold voltage values to read threshold voltage levels of a fresh memory device. In another approach, the read threshold voltage levels of the fresh device are gain adjusted for reading non-gain-adjusted threshold voltage values from the cells which have experienced data retention loss.

Abstract: A handheld device receives a wireless RF transmission that includes multiple video streams and buffers all video streams or selected video streams based on an identification of video streams to buffer. The device might also buffer all or selected audio streams or other real-time data content that is received in the wireless RF transmission. The wireless RF transmission may include a set of video streams (and/or audio streams, and/or other real-timed data) for the handheld device to buffer. A head end that sends the RF transmission may determine which streams to buffer based on operator input, user preferences, and other factors. Alternatively, the handheld device may automatically determine which streams to buffer based on information such as user preferences and information in the RF transmission. Alternatively, a user may select which streams to buffer.

Abstract: The Global Dynamic Critical Path is used to optimize the design of a system-on-a-chip (SoC), where hardware modules are in different clock domains. Control signal transitions of the hardware modules are analyzed to identify the Global Dynamic Critical Path. Rules are provided for handling specific situations such as when concurrent input control signals are received by a hardware module. A configuration of the hardware modules is modified in successive iterations to converge at an optimum design, based on a cost function. The cost function can account for processing time as well as other metrics, such as power consumed. For example, during the iterations, hardware modules which are in the Global Dynamic Critical Path can have their clock speed increased and/or additional resources can be added, while hardware modules which are not in the Global Dynamic Critical Path can have their clock speed decreased and/or unnecessary resources can be removed.

Abstract: Degradation of non-volatile storage elements is reduced by adaptively adjusting erase-verify levels and program-verify levels. The number of erase pulses, or the highest erase pulse amplitude, needed to complete an erase operation is determined. When the number, or amplitude, reaches a limit, the erase-verify level is increased. As the erase-verify level is increased, the number of required erase pulses decreases since the erase operation can be completed more easily. An accelerating increase in the degradation is thus avoided. One or more program-verify levels can also be increased in concert with changes in the erase-verify level. The one or more program-verify levels can increase by the same increment as the erase-verify level to maintain a constant threshold voltage window between the erased state and a programmed state, or by a different increment. Implementations with binary or multi-level storage elements are provided.