Patents Represented by Attorney, Agent or Law Firm Vierra Magen Marcus
  • Patent number: 8121423
    Abstract: Raster segment commands are generated by a delta encoder and are encoded for raster segments detected to have moved in the current frame with respect to a location of the raster segment in a previous frame. Raster segment motion commands are stored in a queue and, when written, copy a raster segment into the current frame from a previous payload or cache. When written from the queue to a payload, raster segment motion commands are applied to a copy of the current frame maintained at the server using a copy of the previous payload sent. When copying a raster segment from a raster segment cache, a raster segment cache command retrieves identified raster segment data from the raster segment cache and copies the raster segment into a particular location in the current frame at the client. The raster segment commands are sent to a client via a payload to copy a raster segment from a previous payload into the current frame at the client or from a raster segment cache to the current frame.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: February 21, 2012
    Assignee: Microsoft Corporation
    Inventor: Brian McDowell
  • Patent number: 8121351
    Abstract: A method includes generating a depth map from at least one image, detecting objects in the depth map, and identifying anomalies in the objects from the depth map. Another method includes identifying at least one anomaly in an object in a depth map, and using the anomaly to identify future occurrences of the object. A system includes a three dimensional (3D) imaging system to generate a depth map from at least one image, an object detector to detect objects within the depth map, and an anomaly detector to detect anomalies in the detected objects, wherein the anomalies are logical gaps and/or logical protrusions in the depth map.
    Type: Grant
    Filed: March 9, 2008
    Date of Patent: February 21, 2012
    Assignee: Microsoft International Holdings B.V.
    Inventors: Sagi Katz, Giora Yahav
  • Patent number: 8121672
    Abstract: Electro static discharge (ESD) protection is provided for electronic devices with integrated circuits, such as for example heart rate monitors. The ESD protection protects against voltage accumulation and discharge through device external parts that are connected to internal device circuitry. The ESD protection isolates the internal device circuitry and provides a low impedance path over which electro static charges and any transient voltages in the device may discharge. The integrated circuits, electrical components, and other parts protected from ESD may be connected to monitor circuitry and be externally exposed, such as sensing or measurement parts exposed outside the device. The external parts may include a sensing case back, sensing push-buttons, or other components that provide a signal to or are otherwise in communication with the internal device circuitry.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: February 21, 2012
    Assignee: Salutron, Inc.
    Inventors: Bill Lau, Thomas Ying-Ching Lo
  • Patent number: 8120399
    Abstract: A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal.
    Type: Grant
    Filed: March 7, 2011
    Date of Patent: February 21, 2012
    Assignee: Rambus Inc.
    Inventor: Jade M Kizer
  • Patent number: 8116140
    Abstract: In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: February 14, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Yingda Dong, Yupin K. Fong, Gerrit Jan Hemink
  • Patent number: 8116139
    Abstract: A power supply and monitoring apparatus such as in a nonvolatile memory system. A power supply circuit provides power to a large number of sense modules, each of which is associated with a bit line and a string of non-volatile storage elements. During a sensing operation, such as a read or verify operation, a discharge period is set in which a sense node of each sense module discharges into the associated bit line and string of non-volatile storage elements, when the string of non-volatile storage elements, is conductive. This discharge sinks current from the power supply, causing a perturbation. By sampling the power supply, a steady state condition can be detected from a rate of change. The steady state condition signals that the discharge period can be concluded and data can be latched from the sense node. The discharge period automatically adapts to different memory devices and environmental conditions.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: February 14, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Tien-chien Kuo, Man L. Mui
  • Patent number: 8110439
    Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: February 7, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Cheeman Yu, Chi-Chin Liao, Hem Takiar
  • Patent number: 8111554
    Abstract: A system is disclosed for programming non-volatile storage that improves performance by setting the starting programming voltage to a first level for fresh parts and adjusting the starting programming voltage as the memory is cycled. For example, the system programs a set of non-volatile storage elements during a first period using an increasing program signal with a first initial value and subsequently programs the set of non-volatile storage elements during a second period using an increasing program signal with a second initial value, where the second period is subsequent to the first period and the second initial value is different than the first initial value.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: February 7, 2012
    Assignee: SanDisk Technologies Inc.
    Inventor: Jeffrey Lutze
  • Patent number: 8109931
    Abstract: A surgical device for preparation of an implant site is disclosed. The device comprises a body capable of being held by a user and an insert that is capable of being coupled to an end of the body. An ultrasound transducer is disposed within the body and provides an ultrasound frequency vibration to the insert in response to an electrical signal. The insert includes a tip having a plurality of cutting elements disposed in a substantially circular configuration. The insert also includes a channel having an opening at the tip for the passage of fluid.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: February 7, 2012
    Assignee: Piezosurgery, Inc.
    Inventors: Tomaso Vercellotti, Domenico Vercellotti, Fernando Bianchetti
  • Patent number: 8111548
    Abstract: A non-volatile storage system stores data by programming the data as binary data into blocks that have not yet been programmed with multi-state data and have not yet been programmed with binary data X times. The system transfers data from multiple blocks (source blocks) of binary data to one block (target block) of multi-state data using a multi-state programming process, where the target block has been previously programmed with binary data X times (or less than X times).
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: February 7, 2012
    Assignee: SanDisk Technologies Inc.
    Inventor: Nima Mokhlesi
  • Patent number: 8111552
    Abstract: A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: February 7, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Jeffrey W. Lutze, Dana Lee
  • Patent number: 8111539
    Abstract: A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and a circuit for detecting the setting and resetting of the reversible resistance-switching elements.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: February 7, 2012
    Assignee: SanDisk 3D LLC
    Inventors: Luca G. Fasoli, Tianhong Yan, Jeffrey Koon Yee Lee
  • Patent number: 8105867
    Abstract: A self-aligned fabrication process for three-dimensional non-volatile memory is disclosed. A double etch process forms conductors at a given level in self-alignment with memory pillars both underlying and overlying the conductors. Forming the conductors in this manner can include etching a first conductor layer using a first repeating pattern in a given direction to form a first portion of the conductors. Etching with the first pattern also defines two opposing sidewalls of an underlying pillar structure, thereby self-aligning the conductors with the pillars. After etching, a second conductor layer is deposited followed by a semiconductor layer stack. Etching with a second pattern that repeats in the same direction as the first pattern is performed, thereby forming a second portion of the conductors that is self-aligned with overlying layer stack lines. These layer stack lines are then etched orthogonally to define a second set of pillars overlying the conductors.
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: January 31, 2012
    Assignee: SanDisk 3D LLC
    Inventors: George Matamis, Henry Chien, James K Kai, Takashi Orimoto, Vinod R Purayath, Er-Xuan Ping, Roy E Scheuerlein
  • Patent number: 8108607
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Grant
    Filed: February 10, 2010
    Date of Patent: January 31, 2012
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Patent number: 8106909
    Abstract: Common key frames are provided to a client during initialization to provide more efficient remoting of user interface graphical information. By storing the common key frames at the client, the common key frames may be loaded quicker and more efficiently at the client without having to resend graphical information for each common key frame each time a common key frame is used to provide a new frame. Differences between a selected common key frame and the new frame are encoded as delta commands. A payload containing a common key frame command, which identifies a common key frame at the client, and delta commands which encode differences between the selected common key frame and new frame is sent to the client. The client receives the payload, sets a cached common key frame as the current frame, applies the delta commands to the selected common key frame, and renders the new frame.
    Type: Grant
    Filed: October 13, 2007
    Date of Patent: January 31, 2012
    Assignee: Microsoft Corporation
    Inventor: Brian McDowell
  • Patent number: 8107298
    Abstract: In a non-volatile storage system, the time needed to perform a programming operation is reduced by minimizing data transfers between sense modules and a managing circuit. A sense module is associated with each storage element. Based on write data, a data node in the sense module is initialized to “0” for a storage element which is to remain in an erased state, and to “1” for a storage element which is to be programmed to a programmed state, then flipped to “0” when programmed is completed. The managing circuit is relieved of the need to access the write data to determine whether a “0” represents a storage element for which programming is completed. Power consumption can also be reduced by keeping a bit line voltage high between a verify phase of one program-verify iteration and a program phase of a next program-verify iteration.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: January 31, 2012
    Assignee: SanDisk Technologies Inc.
    Inventors: Man L. Mui, Pao-Ling Koh, Tien-Chien Kuo, Khanh T. Nguyen
  • Patent number: 8107592
    Abstract: The invention provides in one aspect methods and apparatus for use with C-arm and other CT systems, e.g., with non-rigid geometries. In such systems, by way of example, calibration can be performed to determine the exact position of the x-ray source and the exact orientation of the detector where each projection measurement is made. Next, a weighting coefficient can be determined for the voxels in each plane of a reconstruction volume at every possible projection. Finally, the order in which to process the voxels during image reconstruction can be determined. Following an actual CT scan procedure in which scans are obtained of a volume to be constructed, a system according to these and related aspects of the invention can use an optimal, pre-calculated processing method, while utilizing offsets and weighting coefficients determined during calibration, for performing backprojection image reconstruction.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: January 31, 2012
    Assignee: PME IP Australia Pty Ltd.
    Inventors: Ari P. Berman, Scott A. Thieret, Joseph Goddard
  • Patent number: 8102426
    Abstract: A 3D camera for determining distances to regions in a scene comprising: a photosurface having a plurality of pixels each of which comprises a circuit having a light sensitive element that provides a current responsive to light incident thereon, wherein the circuit comprises, at least one amplifier inside the pixel, having an input and an output; at least one feedback capacitor separate from the light sensitive element and connected between the input and output of each of the at least one amplifier; at least one controllable connection through which current flows from the light sensitive element into the input of the at least one amplifier; a light source; and, a controller that, controls the light source to illuminate the scene with light, opens and closes the at least one controllable connection to gate or modulate current from the light sensitive element of a pixel in the photosurface responsive to the time dependence of the gating or modulation of the light, controls the at least one controllable connectio
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: January 24, 2012
    Assignee: Microsoft International Holdings B.V.
    Inventors: Giora Yahav, Gavriel Joseph Iddan
  • Patent number: 8101981
    Abstract: Back-illuminated, thin photodiode arrays with trench isolation. The trenches are formed on one or both sides of a substrate, and after doping the sides of the trenches, are filled to provide electrical isolation between adjacent photodiodes. Various embodiments of the photodiode arrays and methods of forming such arrays are disclosed.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: January 24, 2012
    Assignee: Array Optronix, Inc.
    Inventors: Alexander O. Goushcha, George Papadopoulos, Perry A. Denning
  • Patent number: 8102698
    Abstract: A memory array having memory cells comprising a diode and a phase change material is reliably programmed by maintaining all unselected memory cells in a reverse biased state. Thus leakage is low and assurance is high that no unselected memory cells are disturbed. In order to avoid disturbing unselected memory cells during sequential writing, previously selected word and bit lines are brought to their unselected voltages before new bit lines and word lines are selected. A modified current mirror structure controls state switching of the phase change material.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: January 24, 2012
    Assignee: SanDisk 3D LLC
    Inventor: Roy E. Scheuerlein