Abstract: A method and system for dynamically selecting accessible banks of memory per cycle within a banked cache memory. In accordance with the method and system of the present invention, the application of power to each bank of memory of a banked cache memory is monitored in order to determine a maximum number of selectable bank accesses per cycle such that power application to each of the banks of memory is not degraded. No more than the maximum number of selectable bank accesses per cycle are permitted for subsequent cycles from among the banks of memory, such that the number of accessible banks of memory of a banked cache memory is dynamically selectable to maximize bank accesses per cycle while maintaining an acceptable power application to each of the banks of memory.

Abstract: A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock is synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip. During boundary scan, the pipelined controls are forced to static levels which are active levels for scanning. Non-pipelined signals control the boundary scan operation based directly on the TCK clock defined in the IEEE 1149.1 boundary scan standard.

Abstract: A method and system for performing problem determination procedures in a hierarchically organized computer system is provided. The hardware components of the data processing system are interconnected in a manner in which the components are organized in a logical hierarchy. A hardware-related error occurs, and the error is logged into an error log file. At some point in time, a diagnostics process is initiated in response to the detection of the error. The logged error may implicate a particular hardware component, and the hardware component of the data processing system is analyzed using a problem determination procedure. In response to a determination that the hardware component does not have a problem, the logically hierarchical parent hardware component of the hardware component is selected for analysis. The logically hierarchical parent hardware component is then analyzed using a problem determination procedure.

Abstract: A method and apparatus for transferring data using an on-chip bus is presented. A data transaction consisting of an address and data packet is transmitted on an on-chip bus which is a two-wire serial bus consisting of an address line and a data line that connects a plurality of satellites in a daisy-chain fashion to a central source. Each on-chip satellite is associated with a unique identifier. In response to a determination that the transaction is accepted by the satellite, which is determined by the address in the address packet positively comparing to a unique identifier for the satellite, the address packet is modified to provide a positive acknowledgment of a receipt of the address packet back to the central source of the transaction. The address packet is modified by clearing the stop bit of the address packet, i.e. gating off or negating the stop bit. Alternatively, the address packet is otherwise modified to indicate the acceptance of the packet.

Abstract: In a multiple machine data processing system, a volume group may be accessed by other than the original owner of the volume group and maintain integrity of the volume group. A logical volume manager on the primary machine holds all incoming I/O requests to the logical volumes in the volume group and waits for all the I/O requests already sent down to the disks in the volume group. Once all the outstanding I/O requests to the disk have been completed, the disks in the volume group are closed and reopened without reserve. The logical volume manager on a secondary machine opens the disks in the volume group without taking a reserve to allow meta-data to be refreshed on the secondary machine. When the secondary machine is finished the disks are closed. The logical volume manager on the primary machine holds all incoming I/O requests to the logical volumes in the volume group and waits for all the I/O requests already sent down to the disks in the volume group.

Abstract: The present invention is a system and method for creating a real-world object as a bitmap image are provided. Initially, the background pixels in the frame buffer are assigned the same color which is different from any color found in the object. A region is created corresponding to the area that the object will occupy. Next, an application window is created on the desktop having borders, title bar, scroll bar, and the like. The size of the window will correspond to the dimensions of the bitmap image. A clipping function is then implemented to remove all of the areas in the application window which do not correspond to the bitmap image.

Abstract: A method for verifying an integrated circuit design includes generating verification coverage information by simulating the operation of the integrated circuit. The verification coverage information is then analyzed to determine a set of missing coverage states. A set of verification directives based on the set of missing coverage states is composed and a set of test cases is generated, based on the verification directives, to simulate the missing coverage states. Analyzing the verification coverage information may include decomposing the verification coverage information into a set of basic coverage tasks (BCTs), wherein each BCT is a generic representation of a corresponding task. Decomposing the verification coverage information into a set of BCTs may comprise decomposing the verification coverage information into a set of covered BCTs and a set of BCT holes, wherein the covered BCTs represent verification states covered by the simulation and BCT holes represent verification states not covered.

Abstract: The invention provides an apparatus and method of allowing a device to respond to a configuration query only if it is the true target of the query. In one embodiment of the invention, logic gates having two inputs are provided. The first input of the logic gates is connected to the signal of a bridge that selects a device when the address of the signal is referenced in the configuration query. The second input of the logic gate receives a signal indicating whether the local bus or the subordinate bus is being configured and the output of the logic gate is used to enable the device. In a second embodiment, certain signals designated to indicate the selection of a bus are used to enable devices to respond to configuration queries.

Abstract: A method and apparatus for reporting a posted speed limit to the driver of a vehicle is disclosed. The position of the vehicle is determined using a GPS receiver or triangulation of cellular telephone signals. The position is used to retrieve speed limit or other information from a database. The information is then reported to the driver. A technique is also disclosed for comparing the actual speed of the vehicle with the posted speed limit and issuing a warning to the driver when the posted speed limit is exceeded.

Abstract: A method of transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data to other devices in the computer system. The computer system identifies, from a plurality of responding devices within the computer system, a target device that contains the data. In response to a determination that the target device does not support higher-performance transactions, the computer system disables higher-performance transactions and transfers the data to the requesting device via a lower-performance transaction process.

Abstract: An error recovery mechanism for an interconnect is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. In response to a parity error occurring on the bus, the bus slave issues a bus parity error response to the bus master via the bus. After waiting for a predetermined number of bus cycles to allow the bus to idle, the bus master then issues a RESTART bus command packet to the bus slave via the bus to clear the parity error. If the RESTART bus command packet is received correctly, the slave bus will remove the parity error response such that normal bus communication may resume.

Abstract: A method for transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data. Each of a plurality of devices within the computer system responds to the request and indicates the location of the device and whether the device contains the requested data. The data is then transferred to the requesting device from one of the devices containing the data within the plurality of devices to the requesting device. The device selected to transfer the data to the requesting device has the closest logical proximity to the requesting device which results in a quick transfer of data.

Abstract: A three-dimensional display apparatus capable of producing an image in three dimensions without the aid of optical illusions or perspective trickery. The display apparatus is comprised of a plurality of pixels which are, in turn, comprised of a plurality of cells. The cells illuminate in one of the three primary colors red, green and blue such that a combination of a red, green and blue cell into a pixel, is capable of producing any color in the visible spectrum. The cells are oriented in the pixel such that light from the pixel is perceivable in six directions, thereby creating a three-dimensional light source. By combining a plurality of these three-dimensional light sources, i.e. a plurality of pixels in a three-dimensional matrix, a three-dimensional image is capable of being displayed.

Abstract: A method of checking for errors in a set associative cache array, by comparing a requested value to values loaded in the cache blocks and determining, concurrently with this comparison, whether the cache blocks collectively contain at least one error (such as a soft error caused by stray radiation). Separate parity checks are performed on each cache block and if a parity error occurs, an error correction code (ECC) is executed for the entire congruence class, i.e., only one set of ECC bits are used for the combined cache blocks forming the congruence class. The cache operation is retried after ECC execution. The present invention can be applied to a cache directory containing address tags, or to a cache entry array containing the actual instruction and data values. This novel method allows the ECC to perform double-bit error as well, but a smaller number of error checking bits is required as compared with the prior art, due to the provision of a single ECC field for the entire congruence class.

Abstract: A method and system for choosing an optimal PCI adapter burst length is disclosed. The optimal burst length is automatically determined by the adapter configuration feature of AIX software using a cache-line size of a PCI bridge and the latency timer value of the target PCI adapter as inputs. The method also provides for a user to be able to override the software-calculated setting.

Abstract: Disclosed is a system and method for enhancing the security of virtual private network (VPN) connections by automatic pre-negotiation of a secondary configuration. If snooping or other security breaches are detected, the VPN tunnel is modified automatically to the secondary pre-arranged configuration, stymieing attempted security violations.

Abstract: A Solid State Disk (“SSD”) and accompanying logic to extend the local memory of an adapter for RAID storage devices. Use of virtual memory, representing the SSD range of addresses in the adapter address memory, allows the adapter to incorporate the total memory into the adapter memory structure. The SSD is non-volatile and large amounts of cache items may be transferred to the SSD as an extension of the adapter memory. The cache write may be delayed and subsequently written to a designated address on a RAID drive, freeing the adapter on-board memory and control functions. Further, the size of the SSD allows for large amounts of data staging and storage, permitting device-to-device communications that would reduce the read and write commands between the host, adapter and drives.

Abstract: There is provided a system for dynamically resynchronizing a storage system made up of a plurality of mirrored logical volumes respectively divided into a plurality of mirrored logical data partitions in the event of a system failure. Immediately after the correction of the problem causing the failure, meals start to resynchronize the plurality of logical volumes but without waiting for the resynchronization to be completed; means access data from a data partition in one of said logical volumes. Then there are means for determining whether the portion of the logical volume containing the accessed partition has already been resynchronized, together with means responsive to these determining means for replacing the corresponding data in the other mirrored partitions in the logical volume with the accessed data, in the event that the portion of the logical volume has not been resynchronized.

Abstract: A Web browser having search capabilities, automatically generates a search list from URLs in the browser's bookmark and/or history files and automatically accesses and searches each URL on the Internet or cache on the browser's computer. Each bookmark or each web page generated for the list, when accessed, may be searched for selected keywords. URL search parameters are entered into the search function, a list of URLs is automatically created from the bookmark file and/or the history file. A new browser is opened and the new browser, in background, accesses the Web or cache, connects when prompted, with each web page listed. Each web page is then searched for keywords provided by a user. Web pages containing the target keywords are then displayed in a format selected by the user on the data processing system display. Individual web pages may be accessed and displayed in successive order by utilizing the graphical “next/previous” buttons present in the web browser window.

Abstract: The present invention discloses a microprocessor bus structure that enables a processor chip to be designed with optional unidirectional or bi-directional I/O buses. The processor is designed with separate input and output bus internal to the chip. A gating network is coupled to these processor uni-directional busses that allows the chip to have an alternate externally wired bus structure. For the lowest cost and lowest performance only one set of bidirectional bus lines are wired external to the chip. These lines have a parallel driver and receiver with appropriate gating to allow the bus to be either in the send or receive mode. The signals from the processor uni-directional input and output buses are wired via appropriate gating to create a single bi-directional bus.