Abstract: A method and apparatus for pipelining clock control signals across a chip. The present invention avoids the need for multiple clock distribution systems by allowing clock controls for clock stopping, scanning, and debugging to be distributed to all local clock buffers through pipelined non-scan latches. The test control pipeline latches may be routed along with the clock through the clock receiver, the central clock buffer, and the sector buffer areas of the chip. A relatively low speed testing mechanism may be used to drive the testing of the chip externally. The test clock control signals are synchronized with a free-running clock on the chip to allow the circuit to be operated at speed during the testing of the chip.

Abstract: A method and system for monitoring the performance of a instruction pipeline is provided. The processor may contain a performance monitor for monitoring for the occurrence of an event within a data processing system. An event to be monitored may be specified through software control, and the occurrence of the specified event is monitored during the execution of an instruction in the execution pipeline of the processor. A particular instruction may be specified to execute within a threshold time for each stage of the instruction pipeline. The specified event may be the completion of a single tagged instruction beyond the specified threshold interval for a stage of the instruction pipeline.

Abstract: There is provided a computer controlled display interface permitting simplified tracking of access time periods to secured data in a user interactive display system with a multitude of displayed windows comprising secured data. A process is provided for tracking for each of said plurality of windows a variable parameter relative to the window, in combination with a process for displaying along at least a portion of the borders of each of said windows a color varying with said variable parameter being tracked for said window. In secured access systems, the parameter being tracked is the period of access time.

Abstract: A method and apparatus for providing evaluation values concerning each position within a specified two-dimensional coordinate range for each position coordinate of each line segment. Such evaluation values are accumulated for each position within the two-dimensional coordinate range. Two-dimensional graphics information is provided according to the accumulated evaluation values. In addition, graphics are displayed according to the two-dimensional graphics information. Because information concerning line segments is accordingly separated from information concerning modeling line segments, hand-written input is enabled for information concerning line segments and a preview is enabled to be performed by use of skeleton information.

Abstract: A method and apparatus for efficiently managing caches with non-power-of-two congruence classes allows for increasing the number of congruence classes in a cache when not enough area is available to double the cache size. One or more congruence classes within the cache have their associative sets split so that a number of congruence classes are created with reduced associativity. The management method and apparatus allow access to the congruence classes without introducing any additional cycles of delay or complex logic.

Abstract: A method for ensuring security of a system accessed utilizing a keypad wherein access is provided to said system via a security code entered on the keypad. A security code is entered on the keypad utilizing a first character configuration of the keypad. Following this, the location of one or more access characters on the keypad is repositioned to present a second character configuration of the keypad. The repositioning of the character configuration is completed electronically in a generally random manner. The change in configuration may take place immediately after each user interface, or after a predetermined number of user interfaces.

Abstract: A cache memory provides a mechanism for storing and retrieving values wherein a hardware mechanism such as a partial address field selector is combined with an software generated selector in order to access specific congruence classes within a cache. Assignment of software generated selectors to specific types of data can be made in order to allow an operating system or application to efficiently manage cache usage.

Abstract: An apparatus and method is provided whereby a monitor module on a token ring network assigns an active monitor and then activates a transmitting module resident on each station on the network to transmit test data frames of varying lengths which have been tuned to encourage maximum phase jitter on the network. Phase jitter related errors are then observed with a dedicated commercially available test apparatus or program.

Abstract: A partitioned cache and management method for selectively caching data by type improves the efficiency of a cache memory by partitioning congruence class sets for storage of particular data types such as operating system routines and data used by those routines. By placing values for associated applications into different partitions in the cache, values can be kept simultaneously available in cache with no interference that would cause deallocation of some values in favor of newly loaded values. Additionally, placing data from unrelated applications in the same partition can be performed to allow the cache to rollover values that are not needed simultaneously.

Abstract: A method of avoiding deadlocks in cache coherency protocol for a multi-processor computer system, by loading a memory value into a plurality of cache blocks, assigning a first coherency state having a higher collision priority to only one of the cache blocks, and assigning one or more additional coherency states having lower collision priorities to all of the remaining cache blocks. Different system bus codes can be used to indicate the priority of conflicting requests (e.g., DClaim operations) to modify the memory value. The invention also allows folding or elimination of redundant DClaim operations, and can be applied in a global versus local manner within a multi-processor computer system having processing units grouped into at least two clusters.

Abstract: A method and system for debugging the execution of an instruction within an instruction pipeline is provided. A processor in a data processing system contains instruction pipeline units. An instruction may be tagged, and in response to an instruction pipeline unit completing its processing of the tagged instruction, a stage completion signal is asserted. An execution monitor external to the pipelined processor monitors the stage completion signals during the execution of the tagged instruction. The execution monitor may be a logic analyzer that displays the stage completion signals in real-time on a display device of the execution monitor. An instruction to be tagged may be selected based upon an instruction selection rule, such as the address of the instruction.

Abstract: A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a plurality of processors that are each associated with a respective one of a plurality of caches. According to the method, a first data item is stored in a first of the caches in association with an address tag indicating an address of the data item. A coherency indicator in the first cache is set to a first state that indicates that the data item is valid. In response to another of the caches indicating an intent to store to the address indicated by the address tag while the coherency indicator is set to the first state, the coherency indicator in the first cache is updated to a second state that indicates that the address tag is valid and that the first data item in the first cache is invalid.

Abstract: A data processing system having a modified processor chip and external components to the processor chip. The processor chip is interconnected to the external components via point-to-point bus connections controlled by an integrated distributed switch (IDS) controller. The IDS controller is placed, during chip design, in the upper layer metals of the processor chip. When the data processing system is a multi-chip multiprocessor data processing system, the IDS controller operates to provide a pseudo switching effect whereby the processor is directly connected to each external component. The IDS controller permits the processor to have greater communication bandwidth and reduced latencies with the external components. It also allows for a connection to distributed external components such as memory and I/O, etc. with overall reduced system components.

Abstract: A method and system for an automated distinguished name lookup is provided for use in a Lightweight Directory Access Protocol (LDAP) directory operation. A user provides input via a dialog window for an identifier string which is not a distinguished name. An LDAP search filter string is generated that contains at least a portion of the identifier string. A directory search is requested using the LDAP search filter string. In response to the requested directory search, one or more distinguished names are received. In response to receiving a single distinguished name for the requested directory search, the received distinguished name is automatically applied in the LDAP directory operation. In response to receiving a plurality of distinguished names for the requested directory search, the plurality of distinguished names are presented to the user, and the user may select one of the plurality of distinguished names.

Abstract: A method and apparatus in a data processing system for displaying resource allocation information. Allocations of a resource are identified. A plurality of cylinders is displayed, wherein each cylinder within the plurality of cylinders provides a graphical representation of an allocation of the resource relative to other cylinders within the plurality of cylinders.

Abstract: A method and system for functional kernel verification testing within a data processing system is described. The method and system of the present invention performs imbedded functional verification test suites on selected kernel components within the data processing system when system administrator kernel component power-on self tests are required during an operating system boot operation. When an error is detected during the imbedded functional verification testing for a selected kernel component, it is reported based on the severity level. For a low or minor functional error, a warning is sent to the user and for a high or major functional error, the data processing system is immediately halted and a service call is generated. Additionally, to correct for the functional error, the data processing system may be enabled to de-install the most recent update of the kernel component.

Abstract: There is provided a system for dynamically resynchronizing, in the even of a system failure, a storage system made up of a plurality of nodes, each which has mirrored logical volumes respectively divided in to a plurality of mirrored logical data partitions. Each of these nodes has the means for accessing a common physical data volume, e.g. a disk drive in which data in corresponding logical volumes at respective nodes is represented by data stored in common in the physical volume. System recovery at the plurality of nodes after a failure at one of the nodes is carried out by commencing the sequential resynchronization of a logical data volume at a nonfailure node to thereby sequentially resynchronize the partitions of the physical data volume representative of the logical data volume, and indicating as resynchronized those portions of the logical data volume at the failure node represented by said resynchronized partitions of the physical data volume.

Abstract: An apparatus for producing object code from source code including input means for receiving the source code, the source code including executable source code and source code documentation, and compilation means, coupled to the input means, including first means for providing object code from the source code, and second means for providing documentation including selected portions of the executable source code and the source code documentation, and for organizing the provided documentation into a predefined format independent of executable source code organization.

Abstract: A data processing system is provided with an electronic key for remote designation of the computer system into a service, secure, or normal/run mode of operation. Such a remote designation is enabled when a physical or manual key is set to a normal/run mode of operation. Setting of the electronic key to a service mode permits remote access to the system for maintenance or debug operations.

Abstract: A method of viewing a directory tree containing logical file system objects residing on a computer system, by displaying a directory tree on a display device of the computer system utilizing a graphical user interface (GUI), expanding a first node of the tree to reveal one or more branches of the first node, and then later expanding a second node of the tree to reveal one or more branches of the second node, wherein the invention automatically collapses the first node of the tree to conceal the one or more branches of the first node in response to the expanding of the second node. This automatic collapsing of other nodes that are not in the path of the selected node thus limits overall expansion of the tree. The setting may be toggled between enabled and disabled states. A pull-down menu can be provided by the GUI which contains the “limit expansion” command.