Patents Represented by Attorney, Agent or Law Firm Vollrath & Associates
  • Small emitter and base-collector bi-polar transistor
    Patent number: 6696342
    Abstract: In a high speed BJT device, the method for producing the device includes forming a self-aligned BJT through the use of a single mask by making use of a single layer of polysilicon. The method includes forming a window in the polysilicon to define a base poly region and an emitter poly region. An underlying oxide/nitride stack is etched in a two etch process to define base and emitter regions for growing a small base and a small emitter. This displays small base-collector and base-emitter junction regions to reduce the capacitance.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: February 24, 2004
    Assignee: National Semiconductor Corp.
    Inventors: Mohamed N. Darwish, Alexei Sadovinkov, Reda Razouk
  • Input clamp circuit for 5V tolerant and back-drive protection of I/O receivers using CMOS process
    Patent number: 6670840
    Abstract: In a receiver input back-drive protection circuit and method, a pass gate is provided between the high pad voltage and the receiver input and a clamping circuit is provided, to present a reduced voltage to the receiver input during stress mode.
    Type: Grant
    Filed: July 26, 2002
    Date of Patent: December 30, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Khusrow Kiani, Elroy M. Lucero
  • Stand-alone triggering structure for ESD protection of high voltage CMOS
    Patent number: 6660602
    Abstract: In a stand-alone snapback NMOS ESD protection structure method of manufacturing, the breakdown voltage is reduced and the structure is made more resilient to hot carrier and soft leakage degradation in the gate region by blocking the NLDD and partially blocking the n+ drain region between the gate and drain region.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: December 9, 2003
    Assignee: National Semiconductor Corp.
    Inventors: Vladislav Vashchenko, Ann Concannon, Peter J. Hopper, Marcel ter Beek
  • Compact ballasting region design for snapback N-MOS ESD protection structure using multiple local N+ region blocking
    Patent number: 6559507
    Abstract: In a n+ snapback device, saturation current is limited by using one or more NLDD current blocking regions.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: May 6, 2003
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Andy Strachan