Patents Represented by Attorney, Agent or Law Firm Wade J. Brady, III
  • Patent number: 8350498
    Abstract: A system includes multiple dynamic current equalizers (DCEs). Each DCE includes a first control loop configured to regulate a current through a circuit branch associated with the dynamic current equalizer. The first control loop includes a first amplifier having two inputs. Each DCE also includes a second control loop configured to regulate a control signal. The second control loop includes a second amplifier having two inputs coupled to the inputs of the first amplifier. The first amplifier has an input offset compared to the second amplifier. The DCEs are configured such that one DCE regulates the control signal while one or more other DCEs regulate the currents through the associated circuit branches based on the control signal. The DCEs can be configured to achieve one or more ratios between multiple currents flowing through multiple circuit branches, where the one or more ratios are defined by resistances coupled to the DCEs.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: January 8, 2013
    Assignee: National Semiconductor Corporation
    Inventor: Hok-Sun Ling
  • Patent number: 8350632
    Abstract: A dipole oscillation tank circuit includes a first capacitive structure, an inductive structure, and a second capacitive structure connected in series. The tank circuit transfers electric energy back and forth between the capacitive structures in dipole oscillation cycles. A renewal circuit injects energy into the tank circuit to replenish energy lost during the oscillation cycles. A switch is connected in parallel across the first capacitive structure and in parallel across the inductive structure and the second capacitive structure. During one phase of the oscillation cycles, the switch is opened for current to flow through the first capacitive structure and the inductive structure, and then closed to bypass the first capacitive structure. During another phase of the oscillation cycles, the switch is closed to bypass the first capacitive structure and then opened for current to flow through the first capacitive structure and the inductive structure.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: January 8, 2013
    Assignee: National Semiconductor Corporation
    Inventor: Jang Dae Kim
  • Patent number: 8350543
    Abstract: A converter controller for discharge of a coil used in a DC/DC converter including a voltage detector connected to monitor a state of a diode connected between the coil and ground and an offset comparator, having an adjustable offset, for causing a coil discharge path to be interrupted. The comparator is provided with an initial high offset so that for at least a first converter switching period, the coil will have sufficient charge when the coil discharge path is interrupted to cause the diode to become forward biased as determined by the voltage detector. The offset is periodically reduced until the coil is sufficiently discharged so that the diode is not forward biased, with that value of offset being optimum and thus used in subsequent switching periods.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: January 8, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Mikko T. Loikkanen, Juha O. Hauru, Ari Kalevi Väänänen
  • Patent number: 8350739
    Abstract: A D/A converter having reference node for receiving a reference voltage and together network having a network reference bus connected to the reference node by way of a first electrical connection. The converter network produces a series of reference outputs derived from the reference voltage in response to a digital input applied to the converter, with the converter network sinking a network reference current at the network reference bus which varies with the converter digital input. A reference current compensator circuit is included which provides a compensation current at the network reference bus having a magnitude which varies in response to at least a portion of the digital input, with the compensation current operating to reduce variations in current through the first electrical connection caused by changes in the digital input.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: January 8, 2013
    Assignee: National Semiconductor Corporation
    Inventor: James Scott Prater
  • Patent number: 8344394
    Abstract: A circuit includes multiple doped regions in a substrate. A first of the doped regions has a tip proximate to a second of the doped regions and is separated from the second doped region by an intrinsic region to form a P-I-N structure. The circuit also includes first and second electrodes electrically coupled to the first and second doped regions, respectively. The electrodes are configured to supply voltages to the first and second doped regions to reverse bias the P-I-N structure and generate light. The first doped region could include multiple tips, the second doped region could include multiple tips, and each tip of the first doped region could be proximate to one of the tips of the second doped region to form multiple P-I-N structures. The P-I-N structure could also be configured to operate in double avalanche injection conductivity mode with internal positive feedback.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: January 1, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Vladislav Vashchenko, Peter J. Hopper, Philipp Lindorfer
  • Patent number: 8347012
    Abstract: An electronic configuration circuit includes a processing circuit (2610) operable for executing instructions and responsive to interrupt requests and operable in a plurality of execution environments (EE) selectively wherein a said execution environment (EE) is activated or suspended, a first configuration register (SCR) coupled to the processing circuit (2610) for identifying the interrupt request as an ordinary interrupt request IRQ when the execution environment (EE) is activated (EE_Active); and a second configuration register (SSM_FIQ_EE_y) for associating an identification of that execution environment (EE) with the same interrupt request, the processing circuit (2610) coupled (5910) to the second configuration register (SSM_FIQ_EE_y) to respond to the same interrupt request as a more urgent type of interrupt request when that execution environment (EE) is suspended (5920).
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: January 1, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Goss, Gregory R. Conti
  • Patent number: 8338082
    Abstract: A method of forming a pattern in a photoresist layer which contains a dye that is insoluble in the developer solution is disclosed. A rinse liquid, typically deionized water, is dispensed onto the substrate while it is rotated at less than 750 rpm. The dye in the exposed regions is carried off by the rinse liquid, and does not accumulate in corners of exposed regions at the edge of the substrate due to centrifugal action.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: December 25, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Maciej Blasiak, Sean Trautman, Jerry Schlesinger
  • Patent number: 8339197
    Abstract: Matched bipolar transistor pairs for use in differential transistor pair circuitry, current mirror transistor pair circuitry and voltage reference transistor pair circuitry are disclosed. Each transistor in the pair includes a base, emitter and a collector region and a doped polysilicon emitter contact, a metal emitter contact and an metal emitter interconnect which makes an electrical connection to the emitter region by way of the metal emitter contact and the polysilicon emitter contact. The metal emitter interconnect is displaced latterly away from the emitter region so that no part of the metal emitter interconnect overlies any portion of the emitter region.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: December 25, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Kwok-Fu Chiu, Yih-Chyi Chong, Michael E. Haslam
  • Patent number: 8329589
    Abstract: A semiconductor device comprises a gate structure on a semiconductor substrate and a recessed region in the semiconductor substrate. The recessed region has a widest lateral opening that is near a top surface of the semiconductor substrate. The widest lateral opening undercuts the gate structure.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Antonio Luis Pacheco Rotondaro, Tracy Q. Hurd, Elizabeth Marley Koontz
  • Patent number: 8331898
    Abstract: An electronic circuit includes a receiver circuit (BSP) operable to perform coherent summations having a coherent summations time interval, and a power control circuit (2130) coupled to said receiver circuit (BSP) and operable to impress a power controlling duty cycle (TON, TOFF) on the receiver circuit (BSP) inside the coherent summations time interval. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.
    Type: Grant
    Filed: October 2, 2008
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Deric Wayne Waters, Karthik Ramasubramanian, Arun Raghupathy
  • Patent number: 8330223
    Abstract: A bipolar transistor has a collector having a base layer provided thereon and a shallow trench isolation structure formed therein. A base poly layer is provided on the shallow trench isolation structure. The shallow trench isolation structure defines a step such that a surface of the collector projects from the shallow trench isolation structure adjacent the collector.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Klaus Schimpf, Manfred Schiekofer, Carl David Willis, Michael Waitschull, Wolfgang Ploss
  • Patent number: 8328585
    Abstract: A multi-layer TiN film with reduced tensile stress and discontinuous grain structure, and a method of fabricating the TiN film are disclosed. The TiN layers are formed by PVD or IMP in a nitrogen plasma. Tensile stress in a center layer of the film is reduced by increasing N2 gas flow to the nitrogen plasma, resulting in a Ti:N stoichiometry between 1:2.1 to 1:2.3. TiN films thicker than 40 nanometers without cracks are attained by the disclosed process.
    Type: Grant
    Filed: August 7, 2009
    Date of Patent: December 11, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Charles Herdt, Joseph W. Buckfeller
  • Patent number: 8324603
    Abstract: Methods and structures provide galvanic isolation for electrical systems using a wide oxide filled trench, and that allows power across the system divide with a transformer, and that transmits data at a high baud rate using an optical link. The system solution allows the integration of all of these elements onto a single semiconductor substrate in contrast to currently available galvanic isolation systems that require multiple individual silicon die that are connected by wire bonds and are relatively slow.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: December 4, 2012
    Assignee: National Semiconductor Corporation
    Inventors: William French, Peter J. Hopper, Vladislav Vashchenko, Philipp Lindorfer
  • Patent number: 8327158
    Abstract: An electronic circuit includes processors (CPU1, CPU2) operable to make respective voltage requests (Vcpu1, Vcpu2), and a power management circuit (1470) having a controllable supply voltage output (VDD1) is coupled to said processors (CPU1, CPU2) and further has a voting circuit (4520) responsive to the voltage requests (Vcpu1, Vcpu2) and operable to automatically establish a function (Fct) of the respective voltage requests (Vcpu1, Vcpu2) to control the controllable supply voltage output (VDD1).
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: December 4, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Patrick C Titiano, Safwan Qasem
  • Patent number: 8324756
    Abstract: A power management (PM) system architecture for a controlled SoC detects availability of power supply for signal-driving at a given node inside a chip, and uses a timer, a discharge mechanism with trigger for starting/stopping a discharge process, and a comparator for monitoring a measured voltage of an intended node during the discharge process. Enabling the discharge mechanism for a known time period helps detection. Power supply can be internally generated in the chip or from a source on board. The architecture detects if the node is driven or floating, an undriven floating node causing a dip in the measured voltage. The measured voltage does not have a dip when the node is driven. The architecture is also configured so that when there is a required on-board external power supply, an internal power supply is disabled to avoid a race-condition. The architecture obviates a dedicated IO pin for mode-indication.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: December 4, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Ranjit Kumar Dash, Lakshmanan Balasubramanian, Anand Devendra Kudari
  • Patent number: 8325752
    Abstract: A circuit for sharing Tx/Rx ports of a CMOS based time multiplexed transceiver includes a Low Noise Amplifier (LNA) and a Power amplifier (PA), and deploys a single RF choke shared between the LNA and PA. The circuit selectively functions as a PA cascode or a LNA input device. In one form the circuit uses MOS transistors configured for use in one of Blue tooth, WLAN and TDMA applications, taking advantage of source-drain symmetry of the MOS transistors. The circuit may include a DC path and be used in WLAN applications, wherein the sharing of the single choke is enabled by one switch in the DC path. As described, the single RF choke is disposed outside of the LNA and the PA. The circuit supports high out powers and causes reduced signal loss due to just one LC tank as opposed to two LC tanks present in the prior art.
    Type: Grant
    Filed: July 29, 2008
    Date of Patent: December 4, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Gireesh Rajendran, Apu Sivadas, Rittu Kulwant Sachdev, Krishnaswamy Thiagarajan
  • Patent number: 8324098
    Abstract: A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: December 4, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Mehmet Emin Aklik, Thomas James Moutinho
  • Patent number: 8318563
    Abstract: A method includes forming a non-continuous epitaxial layer over a semiconductor substrate. The substrate includes multiple mesas separated by trenches. The epitaxial layer includes crystalline Group III nitride portions over at least the mesas of the substrate. The method also includes depositing a dielectric material in the trenches. The method could also include forming spacers on sidewalls of the mesas and trenches or forming a mask over the substrate that is open at tops of the mesas. The epitaxial layer could also include Group III nitride portions at bottoms of the trenches. The method could further include forming gate structures, source and drain contacts, conductive interconnects, and conductive plugs over at least one crystalline Group III nitride portion, where at least some interconnects and plugs are at least partially over the trenches. The gate structures, source and drain contacts, interconnects, and plugs could be formed using standard silicon processing tools.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: November 27, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Sandeep R. Bahl, Abdalla Naem
  • Patent number: 8321489
    Abstract: A novel and useful apparatus for and method of software based phase locked loop (PLL). The software based PLL incorporates a reconfigurable calculation unit (RCU) that is optimized and programmed to sequentially perform all the atomic operations of a PLL or any other desired task in a time sharing manner. An application specific instruction-set processor (ASIP) incorporating the RCU includes an instruction set whose instructions are optimized to perform the atomic operations of a PLL. The RCU is clocked at a fast enough processor clock rate to insure that all PLL atomic operations are performed within a single PLL reference clock cycle.
    Type: Grant
    Filed: September 11, 2007
    Date of Patent: November 27, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Roman Staszewski, Robert B. Staszewski, Fuqiang Shi
  • Patent number: 8309420
    Abstract: A semiconductor structure is provided with (i) an empty well having relatively little well dopant near the top of the well and (ii) a filled well having considerably more well dopant near the top of the well. Each well is defined by a corresponding body-material region (108 or 308) of a selected conductivity type. The regions respectively meet overlying zones (104 and 304) of the opposite conductivity type. The concentration of the well dopant reaches a maximum in each body-material region no more than 10 times deeper below the upper semiconductor surface than the overlying zone's depth, decreases by at least a factor of 10 in moving from the empty-well maximum-concentration location through the overlying zone to the upper semiconductor surface, and increases, or decreases by less than a factor of 10, in moving from the filled-well maximum-concentration location through the other zone to the upper semiconductor surface.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: November 13, 2012
    Assignee: National Semiconductor Corporation
    Inventor: Constantin Bulucea