Patents Represented by Attorney, Agent or Law Firm Wade J. Brady, III
  • Patent number: 8207559
    Abstract: In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N? type or P? type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N? and P? channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET).
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: June 26, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Natalia Lavrovskaya, Saurabh Desai, Alexei Sadovnikov, Zia Alan Shafi
  • Patent number: 8208049
    Abstract: A digital imaging device is provided that includes a high modulation transfer function lens and a multicolor pixel array sensor. The lens is operable to receive an incoming signal and to provide a focused signal based on the incoming signal. The multicolor pixel array sensor, which is adjacent to the lens, is operable to receive the focused signal from the lens and to generate a sensor signal based on the focused signal. The device may also include an interpolator coupled to the multicolor pixel array sensor. The interpolator is operable to receive the sensor signal from the multicolor pixel array sensor and to interpolate the sensor signal to generate an interpolated signal.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: June 26, 2012
    Inventor: Thomas W. Osborne
  • Patent number: 8203199
    Abstract: A semiconductor chip package having multiple leadframes is disclosed. Packages can include a first leadframe having a first plurality of electrical leads and a die attach pad having a plurality of tie bars, a second leadframe generally parallel to the first leadframe and having a second plurality of electrical leads, and a mold or encapsulant. Tie bars can be located on three main sides of the die attach pad, but not the fourth main side. Gaps in the first and second plurality of electrical leads can be enlarged or aligned with each other to enable the elimination of mold flash outside the encapsulated region, which can be accomplished with mold cavity bar protrusions. Additional components can include a primary die, a secondary die, an inductor and/or a capacitor. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes.
    Type: Grant
    Filed: December 10, 2009
    Date of Patent: June 19, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Lee Han Meng Eugene Lee, Kuan Yee Woo
  • Patent number: 8204107
    Abstract: A novel and useful apparatus for and method of reducing phase and amplitude modulation bandwidth in polar transmitters. The bandwidth reduction mechanism of the present invention effectively reduces the phase modulation bandwidth of the polar modulation performed in the transmitter by modifying the zero-crossing trajectories in the IQ domain. This significantly reduces the phase modulation bandwidth while still meeting the output spectrum and error vector magnitude (EVM) requirements of the particular modern wideband wireless standard, such as 3G WCDMA, etc. The mechanism detects a zero crossing or a near zero crossing within a predetermined threshold of the origin and an offset vector is generated that when added to the input TX IQ data, shifts the trajectory to avoid the origin thus reducing the resultant polar modulation amplitude and phase bandwidth.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: June 19, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Jingcheng Zhuang, Robert B. Staszewski, Khurram Waheed
  • Patent number: 8200879
    Abstract: A semiconductor device includes an interface controller for communication with a memory device over a communication link. The link includes a plurality of data lines for transmitting data. A plurality of bus width values are defined, each being a selectable number of data lines over which data are to be transmitted. The number of data lines is in the range between one and the number of the plurality of data lines. The interface controller is dynamically configurable to any of the defined bus width values, which becomes the current bus width. The transmission over each data line may be selectably in either direction. The transmission over all data lines corresponding to the current bus width may collectively carry, in at least one direction, command codes, memory addresses, and data in an intermixed manner.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: June 12, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Ohad Falik, Leonid Azriel
  • Patent number: 8198150
    Abstract: A low thermal pathway is provided from the top surface of a silicon substrate to the bottom surface of the silicon substrate by first forming aluminum plugs in the bottom surface of the silicon substrate that contact the silicon substrate and extend up towards the top surface, and then heating the aluminum plugs to a temperature for a period of time sufficient to cause spikes to grow from the sides of the aluminum plugs.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: June 12, 2012
    Assignee: National Semiconductor Corporation
    Inventor: Visvamohan Yegnashankaran
  • Patent number: 8198708
    Abstract: A system and method is disclosed for improving complementary metal oxide semiconductor (CMOS) compatible non volatile memory (NVM) retention reliability in memory cells. A memory cell of the invention comprises a backend layer that reduces charge leakage from a floating gate of the memory cell. A first bottom portion of the backend layer is formed from a first layer of silicon oxynitride having a low value of defect/trap density. A second top portion of the backend layer is formed from a second layer of silicon oxynitride having a high value of defect/trap density. The first layer of silicon oxynitride inhibits electron transport and the second layer of silicon oxynitride protects CMOS devices from plasma induced damage.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: June 12, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Jiankang Bu, Henry G. Prosack, Jr., David Courtney Parker, Heather McCulloh
  • Patent number: 8193603
    Abstract: A semiconductor structure is formed in the metal interconnect structure of an integrated circuit in a method that provides either two individual resistors that are vertically isolated from each other, or a metal-insulator-metal (MIM) capacitor. As a result, both semiconductor resistors and MIM capacitors can be formed in the same process flow.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: June 5, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Jeffrey Klatt
  • Patent number: 8193602
    Abstract: A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: June 5, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Zia Alan Shafi, Jeffrey A. Babcock
  • Patent number: 8193798
    Abstract: A method includes generating a drive signal for a transistor in a switching regulator. The drive signal turns the transistor on and off to generate a regulated output voltage. The drive signal is generated based on a clock signal. The method also includes dynamically decreasing a frequency of the clock signal to decrease a dropout voltage of the switching regulator. Dynamically decreasing the frequency of the clock signal can increase a duration of switching periods defined by the clock signal. The dropout voltage could have a first value proportional to TOFF—MIN/TON—MAX during shorter switching periods and a second value proportional to TOFF—MIN/TON—MAX—DFC during longer switching periods. TOFF—MIN represents a minimum amount of off-time for the transistor during each switching period, TON—MAX represents a maximum amount of on-time for the transistor during shorter switching periods, and TON—MAX—DFC represent a maximum amount of on-time for the transistor during longer switching periods.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: June 5, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: W. David Pace, Robert H. Bell, Steven L. Harris
  • Patent number: 8194892
    Abstract: First and second channel bridge amplifiers are dynamically configured to drive either speakers or headphones. The first channel bridge amplifier includes a first amplifier driving one end of a first speaker through a mechanical switch in a headphone-jack, and a second amplifier driving another end of the first speaker. The second channel bridge amplifier includes third and fourth amplifiers driving respective ends of a second speaker. An amplifier control circuit dynamically detects the insertion or removal of a plug in the jack and configures the amplifiers accordingly. When a plug is inserted into the jack, the mechanical switch disconnects the first speaker from the first amplifier, and the fourth amplifier is tri-stated disconnect the second speaker. The first and third amplifiers are configured to drive the first and second channels of the headphones, while the third amplifier drives the headphone common point (shield ring) as a virtual ground connection.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: June 5, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Kazim Seven
  • Patent number: 8189881
    Abstract: A fingerprint sensor uses beams of light to detect a fingerprint as the finger is swiped over a ridged surface. The beams of light are directed toward individual regions of the ridged surface so that the light beams will generally be totally internally reflected when a finger is not touching the ridge. The total internal reflection characteristics of the ridged surface are altered at regions touched by the ridges on the finger as the finger is swiped over the sensor. This alters the amount of light reflected by the ridged surface. These changes in light reflection as the finger is swiped over the ridged surface can be observed simultaneously over multiple channels, preferably disposed laterally with respect to each other, to provide a fingerprint.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: May 29, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Gerard Dirk Smits
  • Patent number: 8187920
    Abstract: One aspect of the present invention relates to an integrated circuit package that includes multiple layers of a planarizing, photo-imageable epoxy that are formed over a substrate. In some designs, the substrate is a silicon wafer. An integrated circuit is embedded in the epoxy. An antenna, which is electrically coupled to the active face of the integrated circuit through an interconnect layer, is formed over one of the epoxy layers. In various embodiments, at least some of the epoxy layers are positioned between the substrate and the antenna such that there is a distance of at least approximately 100 microns between the substrate and the antenna.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: May 29, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Anuraag Mohan, Peter Smeys
  • Patent number: 8183621
    Abstract: The number of times that a non-volatile memory (NVM) can be programmed and erased is substantially increased by utilizing a localized heating element that anneals the oxide that is damaged by tunneling charge carriers when the NVM is programmed and erased. The program and erase voltages are also reduced when heat from the heating element is applied prior to programming and erasing.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: May 22, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey A. Babcock, Yuri Mirgorodski, Natalia Lavrovskaya, Saurabh Desai
  • Patent number: 8179775
    Abstract: An electronic device includes a first circuit (111) operable to generate a precoding matrix index (PMI) vector associated with a plurality of configured subbands, and further operable to form a compressed PMI vector from the PMI vector wherein the compressed PMI vector includes one reference PMI and at least one differential subband PMI defined relative to the reference PMI; and a second circuit (113) operable to initiate transmission of a signal communicating the compressed PMI vector. Other electronic devices, processes and systems are also disclosed.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: May 15, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Runhua Chen, Eko N. Onggosanusi
  • Patent number: 8171333
    Abstract: Multi-channel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system in which sub-beam signals are formed by delaying sub-beam pulse pattern data in accordance with sub-beam pulse delay data and multiple clock signals.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: May 1, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Wei Ma, Zhenyong Zhang, Jian-yi Wu
  • Patent number: 8150335
    Abstract: A Cartesian transmitter and a method of linearizing a Cartesian transmitter. In one embodiment, the transmitter includes: (1) a transmit chain configured to receive an input signal having in-phase and quadrature components and having a predistorter configured to employ at least one compensation lookup table to carry out in-phase and quadrature compensation predistortion with respect to the input signal, a combiner configured to combine outputs of the predistorter and a nonlinear element configured to process an output of the combiner, (2) a receiver coupled to the transmit chain and (3) predistortion compensation circuitry associated with the receiver and configured to update the at least one compensation lookup table based on the input signal and a signal from the receiver.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: April 3, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Khurram Waheed, Seydou N. Ba
  • Patent number: 8150336
    Abstract: A polar transmitter and a method of linearizing a polar transmitter. In one embodiment, the transmitter includes: (1) a transmit chain having a predistorter configured to employ first amplitude and phase compensation lookup tables to carry out predistortion in the transmit chain, (2) a receiver coupled to the transmit chain and (3) predistortion compensation circuitry associated with the receiver and configured to update second amplitude and phase compensation lookup tables associated therewith based on at least one signal from the transmit chain, the values in the updated second amplitude and phase compensation lookup tables thereby available for subsequent predistortion.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: April 3, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Khurram Waheed, Seydou N. Ba
  • Patent number: 8149252
    Abstract: A display uses x illuminator systems to produce x primary colors and y overlap colors, which are combinations of primary colors, to illuminate a spatial light modulator in a display system. A first set of n duty cycles for the x primary colors over a frame is provided, wherein the display system can select any one of the duty cycles to produce a desired white point. A second set of n duty cycles of x+y colors over a frame corresponding to the first set of duty cycles is determined, where the second set of duty cycles are generated responsive to a specified desired allocation of the frame to the y overlap colors, such that each of the overlap colors can be displayed from a dark shade to a bright shade while maintaining a constant color point.
    Type: Grant
    Filed: May 22, 2008
    Date of Patent: April 3, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Todd Alan Clatanoff
  • Patent number: 8138806
    Abstract: Driver circuit for high voltage differential signaling. The circuit includes a first positive driver that generates a first positive transition at a first output in response to an input. The circuit also includes a first current element coupled to the first positive driver to enable generation of a current. Further, the circuit includes a first negative driver coupled to the first current element, and responsive to the input and the current, due to the first current element, to generate a first negative transition, at a second output, at a rate similar to that of the first positive transition.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: March 20, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Jayesh Gangaprasad Wadekar, Sumantra Seth, Kartik Reddy