Patents Represented by Attorney Wagner, Murabito & Hao LLP
  • Patent number: 7117421
    Abstract: The present invention provides flexible and efficient memory configuration that is capable of economically addressing both resource consumption and ECC concerns. A memory system facilitates transparent ECC operations without dedicated ECC connections. A first dynamic random access memory structure stores data, wherein the data connections to the memory system are limited to the width of the first dynamic random access memory structure. A second dynamic random access memory structure dedicated to storing error correction code information, wherein the error correction code information is accessed via the data connections. In one exemplary implementation, the first memory structure and the second memory structure the data and ECC are included in the same memory bank. In an alternate implementation, the first memory structure and the second memory structure the data and ECC are included in the different memory banks and are accessed in parallel.
    Type: Grant
    Filed: May 31, 2002
    Date of Patent: October 3, 2006
    Assignee: Nvidia Corporation
    Inventor: Radoslav Danilak
  • Patent number: 7098634
    Abstract: An enhancement mode JFET as a switching device in a buck-boost converter circuit combined with a single rectifier diode and an inductor. A control circuit coupled to the gate of the JFET switches the JFET between a current conducting state and a current blocking state. The ratio of converter output voltage to converter input voltage is determined by the ratio of JFET current blocking time to the sum of JFET conduction time and JFET blocking time. This pulse width modulation scheme is thus used to adjust the dc output voltage level.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: August 29, 2006
    Assignee: Lovoltech, Inc.
    Inventor: Ho-Yuan Yu
  • Patent number: 7075132
    Abstract: A programmable junction field effect transistor (JFET) with multiple independent gate inputs. A drain, source and a plurality of gate regions for controlling a conductive channel between the source and drain are fabricated in a semiconductor substrate. A first portion the gate regions are coupled to a first gate input and a second portion of the gate regions are coupled to a second gate input. The first and second gate inputs are electrically isolated from each other. The JFET may be programmed by applying a programming voltage to the first gate input and operated by applying a signal to the second gate input.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: July 11, 2006
    Assignee: Lovoltech, Inc.
    Inventors: Chong Ming Lin, Ho Yuan Yu
  • Patent number: 7068256
    Abstract: A portable computer system contained within a housing that comprises an electronic muscle material for performing a plurality of functions. The electronic muscle can sense when the portable computer is being handled. When handled, the electronic muscle material can cause the portable computer system to enter a power-on mode and, conversely, when no longer being handled it can cause the portable computer system to exit the power-on mode. When handled, the electronic muscle material can further detect the left- or right-handedness of the user and, based on the handedness, can generate function buttons or other alterations to accommodate the user's hand preference and finger placement. The placement of the user's hand in a location on the electronic muscle material which indicates preparation to write can activate a selectable graffiti display area on the touch screen.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: June 27, 2006
    Assignee: Palm, Inc.
    Inventors: Shawn Gettemy, Yoon Kean Wong
  • Patent number: 7058732
    Abstract: A method and apparatus for automatically detecting the memory size of a serial peripheral interface (SPI) device. Specifically, the present invention describes an SPI interface circuit including a memory controller chip, an EEPROM, a sensing circuit, and a pulldown resistor. In one embodiment, a “READ” command from the controller to the SPI device is sent in a first byte of information transferred between the controller and SPI device. The data Input/Output (D-IO) pin is then driven low for the second byte of information. Next, the D-IO pin is floated and the pin assumes a logic “0” level due to a pulldown resistor. Subsequently, a sensing circuit can detect when and if a non-zero data value passes from the SPI device to the memory controller chip to determine the memory size of the SPI device or the absence of an SPI device.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: June 6, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventor: Lane Hauck
  • Patent number: 7051152
    Abstract: A data storage system using compression to increase performance. The system has a hardware compression/decompression engine for performing data compression on a data block and performing data decompression of the data block. A controller is coupled to the hardware compression/decompression engine and is for storing compressed data of the data block in a primary region of a data storage device and is further for storing any overflow from the primary region in an overflow region of the data storage device. The overflow region is dedicated to the primary region. There may be a number of such primary regions and a number of such secondary regions, with the secondary regions mapped one-to-one to the primary regions.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: May 23, 2006
    Assignee: nVidia Corporation
    Inventor: Radoslav Danilak
  • Patent number: 7046039
    Abstract: A class AB analog inverter comprising cascoded n-channel (NMOS) and p-channel (PMOS) transistors. The inverter uses complementary devices, of which one or more may be a first transistor in cascode with a second transistor. The first and second transistors may have the same threshold voltage (VT), or may have different threshold voltages. The class AB inverter provides improved slew rate and low power capabilities for use in mixed-signal integrated circuits such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and active filters.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: May 16, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Adrian B. Early, Harold M. Kutz
  • Patent number: 7035886
    Abstract: A re-configurable combinational logic device. The device comprises combinational logic that inputs a number of signals and a memory array for storing data to define Boolean expressions for a number of states. The states have Boolean expressions of selected signals of the signals input to the combinational logic. The combinational logic is configurable, in response to the data, to select the signals as operands for said Boolean expression and to output a signal that is the result of the Boolean expression. The combinational logic is re-configurable, in response to further data from the memory array, to output a signal that is the result of additional Boolean expressions.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: April 25, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Craig Nemecek, Steve Roe
  • Patent number: 7013058
    Abstract: The present invention is an efficient system and method for cascading optical switches. A plurality of cascaded optical switches form a cascaded optical switch fabric and direct an optical signal beam from one of the plurality of optical switches to another of the plurality of optical switches. In one embodiment of the present invention, a fixed incidence corrective device is included in a cascaded optical switch fabric. The incidence corrective device directs an optical signal beam in a shallow angle so that it strikes the next optical switch at a corrected incidence angle. A corrected incidence angle permits an optical signal beam to be forwarded at a relatively shallow angle to an optical switch located in a relatively close proximity on the optical switch fabric. The present invention also provides for refocusing of spreading optical signal beams and mitigation of signal loss.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: March 14, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventor: Dinesh Maheshwari
  • Patent number: 7009228
    Abstract: A method for fabricating a guard ring structure for JFETs and MESFETs. Trenches are etched in a semiconductor substrate for fabrication of a gate structure for a JFET or MESFET. At time the gate trenches are etched, concentric guard ring trenches are also etched. The process used to fabricate the gate p-h junction or Schottky barrier at the bottom of the gate trenches is also used to fabricate the guard ring at bottom of the guard ring trenches. The separation between the guard ring trenches is 1.0 to 3.0 times greater than the separation between the gate trenches.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 7, 2006
    Assignee: Lovoltech, Incorporated
    Inventor: Ho-Yuan Yu
  • Patent number: 7010724
    Abstract: Circuitry for detecting operating system hang conditions is provided. The circuitry includes interrupt logic for receiving system interrupts targeted for a central processing unit. Further included is hang detection logic that is in communication with the interrupt logic. The hang detection logic is capable of determining whether the central processing unit has processed an interrupt within a period of time. Hang resolution logic is further provided for removing the central processing unit from a hang state when it is determined that the interrupt has not been processed within the period of time.
    Type: Grant
    Filed: June 5, 2002
    Date of Patent: March 7, 2006
    Assignee: Nvidia Corporation
    Inventor: Gary D. Hicok
  • Patent number: 7005347
    Abstract: In a trench-gated MIS device contact is made to the gate within the trench, thereby eliminating the need to have the gate material, typically polysilicon, extend outside of the trench. This avoids the problem of stress at the upper corners of the trench. Contact between the gate metal and the polysilicon is normally made in a gate metal region that is outside the active region of the device. Various configurations for making the contact between the gate metal and the polysilicon are described, including embodiments wherein the trench is widened in the area of contact. Since the polysilicon is etched back below the top surface of the silicon throughout the device, there is normally no need for a polysilicon mask, thereby saving fabrication costs.
    Type: Grant
    Filed: April 27, 2004
    Date of Patent: February 28, 2006
    Assignee: Vishay-Siliconix
    Inventors: Anup Bhalla, Dorman Pitzer, Jacek Korec, Xiaorong Shi, Sik Lui
  • Patent number: 7007117
    Abstract: A method and system for automatically identifying the type of communication interface used to couple a portable computer system with a second computer system, and for selecting the form of an application that is used with the type of interface. For example, a debugger application is collaboratively executed on the computer systems over the interface. When entering the debugger mode, software executed on the portable computer system identifies the type of interface by reading a resistance value of a pin. After determining the type of interface, the form of the debugger used with the interface is automatically selected. A similar process is followed for other applications that depend on the type of interface. The user does not have to manually identify the type of interface. Instead, in response to a command that is independent of the type of interface, the proper form of the application is automatically selected.
    Type: Grant
    Filed: November 29, 2000
    Date of Patent: February 28, 2006
    Assignee: palmOne, Incorporated
    Inventors: James B. Henrie, Edward Endejan, Adam Hampson
  • Patent number: 7003732
    Abstract: A method and system of automatically generating information in a grid structure on a display screen. In one embodiment, the present invention is directed to displaying and editing microcontroller chip configuration information. The method involves reading a data file describing a configurable sub-system of the microcontroller, identifying the configurable parameters of the sub-system and constructing a two dimensional display for displaying the values of variables associated with those parameters. The two dimensional display (“display grid”) may contain a row for each parameter, a column for the name of the parameter, and a cell in each row for each variable associated with that parameter. The cells associated with variables can be restricted to accept values chosen from a set enumerated in the data file describing the configurable sub-system.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: February 21, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventor: Marat Zhaksilikov
  • Patent number: 7002569
    Abstract: A method and system for enhancing the life of a battery within a portable or otherwise battery operated electronic device. The method and system provide user selectable display modes, e.g., from color to monochrome, that can be changed in order to enhance the life of the device's battery. The monochrome display mode can be selected by the user when the battery level is detected below a predefined threshold. In one embodiment, the electronic device is a hand held computer system with a display device. When the battery level is detected as below a preselected level, a message is generated on the computer display screen. The message informs the user that the display mode of the screen can be changed to enhance the battery life. If selected, the display mode can change from color to monochrome thereby saving power because the monochrome display does not utilize a back-lighting element. In one embodiment, color sequential techniques are used to provide a flat panel color display.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: February 21, 2006
    Assignee: Palm, Inc.
    Inventors: Shawn Gettemy, Anthony Kim
  • Patent number: 6995052
    Abstract: A method for fabricating a junction field effect transistor (JFET) with a double dose gate structure. A trench is etched in the surface of a semiconductor substrate, followed by a low dose implant to form a first gate region. An anneal may or may not be performed after the low dose implant. A gate definition spacer is then formed on the wall the trench to establish the lateral extent of a second, high dose implant gate region. After the second implant, the gate is annealed. The double dose gate structure produced by the superposition of two different and overlapping regions provides an additional degree of flexibility in determining the ultimate gate region doping profile. A further step comprises using the gate definition spacer to define the walls of a second etched trench that is used to remove a portion of the p-n junction, thereby further reducing the junction capacitance.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: February 7, 2006
    Assignee: Lovoltech, Inc.
    Inventors: Ho-Yuan Yu, Valentino L. Liva, Pete Pegler
  • Patent number: 6992659
    Abstract: An integrated enclosure/touch screen assembly. A touch screen assembly consisting of a display mechanism and optical sensor mechanism are enclosed within a single piece cover. The optical sensor mechanism consists of lens structure and optical sensor couple to the lens structure. The single piece cover includes a transparent top surface and the lens structure is embedded within the transparent top surface. The transparent top surface of the single piece cover provides an enclosure that is both dust free and waterproof. The lens structure of the single piece cover functions by columnating light across the transparent surface. The optical touch sensor is coupled to the lens structure to register contact with the transparent surface via the lens structure by detecting disturbances in the columnated light. In one embodiment, the single piece cover is constructed by embedding the lens structure directly into the transparent surface.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: January 31, 2006
    Assignee: palmOne, Inc.
    Inventor: Shawn R. Gettemy
  • Patent number: 6990533
    Abstract: Restoring basic functionality to a portable computer system via a server accessed remotely by telephone. A user of a portable computer system which has lost data and software which was held in volatile memory may connect to a server to restore basic functionality to the portable computer system. The server may be an enterprise or a web-based server. The connection may be made, for instance, over a 1-800 or a 1-900 telephone line. The server transfers sufficient software to the RAM of the portable computer for it to regain basic functionality. For example, synchronization software may be transferred to the portable computer. The portable computer may then use the synchronization software to synchronize via the server or host connection more fully in order to restore lost data or lost software applications that were stored on a server or on a host computer system.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: January 24, 2006
    Assignee: Palm Source, Inc.
    Inventor: David Creemer
  • Patent number: 6990658
    Abstract: A method for use by a host microprocessor which translates sequences of instructions from a target instruction set for a target processor to sequences of instructions for the host microprocessor including the steps of beginning execution of a speculative sequence of target instructions by committing state of the target processor and storing memory stores previously generated by execution at a point in the execution of instructions at which state of the target processor is known, executing the speculative sequence of host instructions until another point in the execution of target instructions at which state of the target processor is known, rolling back to last committed state of the target processor and discarding the memory stores generated by the speculative sequence of host instructions if execution fails, and beginning execution of a next sequence of target instructions if execution succeeds.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: January 24, 2006
    Assignee: Transmeta Corporation
    Inventors: Linus Torvalds, Robert Bedichek, Stephen Johnson
  • Patent number: D515086
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: February 14, 2006
    Assignee: Nvidia Corporation
    Inventors: Michael B. Diamond, Cesar Carrera