Abstract: The present invention system and method provides voltage level support for an output target signal (e.g., a dynamic node output signal) that “keeps” the output target signal at a particular voltage level with efficient suspension of the voltage level maintenance or support during an evaluation transition period (e.g., a read operation) of the output target signal.

Abstract: A miniature keyboard wherein the keys are arranged in a way to improve data entry and decrease the chance of depressing multiple keys at a time. Accordingly, the height of the keys are patterned to decrease the chance of multiple key depressions thus increasing the accuracy of data input into the personal digital assistant. In one embodiment, the height of the keys is alternated down the individual rows of keys. In another embodiment, the height of the keys is alternated across individual columns of keys. Similarly, in another embodiment, the heights of the keys are arranged in a checkered pattern on the keyboard. In addition, another embodiment staggers the heights of the keys and incorporates embodiments mentioned above. By incorporating different key arrangements and alternating the height of the keys, key differentiation, key navigation, and data input accuracy is greatly improved due to the improved tactile feedback provided by the miniature keyboard.

Abstract: Declarative markup languages for speech applications such as VoiceXML are becoming more prevalent programming modalities for describing speech applications. Present declarative markup languages for speech applications model the running speech application as a state machine with the program specifying the transitions amongst the states. These languages can be extended to support a marker-semantic to more easily solve several problems that are otherwise not easily solved. In one embodiment, a partially overlapping target window is implemented using a mark semantic. Other uses include measurement of user listening time, detection and avoidance of errors, and better resumption of playback after a false barge in.

Abstract: Diagonal deep well region for routing the body-bias voltage for MOSFETS in surface well regions is provided and described.

Abstract: A method and system of temperature compensated integrated circuits. Operating characteristics of integrated circuitry are enhanced by application of temperature compensation.

Abstract: An integrated back-end integrated circuit (IC) manufacturing assembly is disclosed. In one embodiment, the present invention has a front-of-line portion comprising a plurality of integrated sub-stations for operating on a first plurality of die-strips on an in-line basis to produce a second plurality of die-strips. The present embodiment further comprises an end-of-line portion coupled to the front-of-line portion and comprising a plurality of integrated sub-stations for operating on the second plurality of die-strips on an in-line basis to produce die-strip components. The present embodiment also comprises an in-line test portion coupled to the end-of-line portion for testing the die-strip components. The present embodiment further comprises a finish portion coupled to the in-line test portion and comprising a plurality of integrated sub-stations operating on tested die-strip components.

Abstract: A circuit and method for distributing events in an event stream. A circuit for distributing events in a signal into a plurality of channels of circuitry capable of timestamping events is described. The circuit includes a first plurality of flip-flops arranged in a cascading configuration. The cascading configuration distributes a primary event stream into a first plurality of secondary event streams on each successive rising edge of the primary event stream. The circuit also includes a second plurality of flip-flops arranged in another cascading configuration for distributing the primary event stream. The primary event stream is distributed into a second plurality of secondary event streams on each successive falling edge of said primary event stream.

Abstract: A method and system for automatic power-up and automatic power-down of a computer system based on the position and/or rotation of an associated stylus and/or hinge. In one embodiment, the computer system is a portable computer having a logic board, a display screen, a digitizer and a receiving slot for an associated stylus. When the stylus is removed from the receiving slot, a switch automatically turns full power onto the computer system thereby allowing a user full use of the computer without requiring an on/off button to be pressed. When the stylus is inserted back into the receiving slot, the switch automatically returns the computer to a power reduction mode where one or all of the components of the computer are powered down. Again, the power reduction mode is entered without requiring the user to press the on/off button. The switch can be made of a single detector or a dual detector combination and can be of a mechanical, electromagnetic, optical or electrical nature.

Abstract: JFET and MESFET structures, and processes of making same, for low voltage, high current and high frequency applications. The structures may be used in normally-on (e.g., depletion mode) or normally-off modes. The structures include an oxide layer positioned under the gate region which effectively reduces the junction capacitance (gate to drain) of the structure. For normally off modes, the structures reduce gate current at Vg in forward bias. In one embodiment, a silicide is positioned in part of the gate to reduce gate resistance. The structures are also characterized in that they have a thin gate due to the dipping of the spacer oxide, which can be below 1000 angstroms and this results in fast switching speeds for high frequency applications.

Abstract: Embodiments of the present invention provide a memory controller comprising a front-end module, a back-end module communicatively coupled to the front-end module, and a physical interface module communicatively coupled to the back-end module. The front-end module generates a plurality of page packets from a plurality of received memory commands, wherein the order of receipt of said memory commands is preserved. The back-end module dynamically issues a next one of the plurality of page packets while issuing a current one of the plurality of page packets. The physical interface module causes a plurality of transfers according to the dynamically issued current one and next one of the plurality of page packets.

Abstract: A disk storage system having servo data stored thereon for accurate head position control over a magnetic or other storage medium. The servo data is seamless and untrimmed and consists of a primary servo burst set (AB burst) that defines the desired tract pitch for the surface. Multiple secondary servo burst sets (e.g., CD burst and EF burst) are written at the desired track pitch but radially offset from the primary burst set. The servo data is written in multiple servo sectors around the surface of the medium. From the servo data, PES (position error signals) are generated for providing linear position sensitivity information to the head position control logic. The resulting PES is more linear for smaller head sizes.

Abstract: A multimedia decoder unit having error concealment and fast muting capabilities. The audio decoder provides error concealment using a dynamic recovery delay that is based on the error rate of an input digital bitstream and also uses frame repeating. The decoder allows fast audio muting whereby audio can be muted within two audio frames of a mute signal that immediately freezes the video frame, e.g., a channel change. With respect to the dynamic recovery delay, a template of fixed length is used to inspect the last frames within the template. If error is found, then the error sum is used as an index into a table length which provides a dynamic template length. Error within the dynamic template length is computed and if larger than a tolerance, the current frame is muted. This allows the recovery delay to be adaptive and based on the error rate while still allowing mute merging.

Abstract: A cover for an electronic device made of a transparent material and having a form factor that protects function buttons of the device from inadvertent actuation. The cover has an opening of a size, shape and location to afford access to an interface device for multi-way navigation with the cover in place. Protrusions in tabs at the sides of the cover snap into cutouts located midway along the side of the electronic device and may be used to hold the cover in place. The cover may be stored on the back of the device while the device is in use. The transparent nature of the cover affords viewing of a display screen with the cover in place.

Abstract: A method of programming a programmable analog device that introduces on a single chip a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. Configuration registers define the type of function to be performed, the way in which the analog blocks are to be coupled, the inputs and outputs of the analog blocks, and the characteristics of the analog elements. The configuration registers can be dynamically programmed. Thus, the device can be used to realize a large number of different analog functions and applications.

Abstract: Frequency correction of a radio module. Multiple samples of frequency data are taken during a quiescent portion of the base station transmission, to estimate the amount of frequency correction needed. An embodiment applies the frequency data to a median filter to eliminate invalid data. Next, a new reference frequency is applied to a radio transceiver in the radio module to provide the frequency correction. If the frequency was corrected by greater than a pre-determined amount, the process performs a large shift frequency correction, including verifying that the first frequency correction was satisfactory and verifying that the radio transceiver is able to receive data after the frequency correction has been performed. If the frequency was corrected by smaller than a pre-determined amount, the process performs a small shift frequency correction, including updating a total of all frequency corrections made since a stored reference frequency was updated.

Abstract: A method and system for selecting and controlling target devices on a digital home network, in particular a network compliant with IEEE 1394. Various aspects of the process for connecting target devices are moved from the controller to the target devices. An input-select button is used to select a device (a source device) to provide an input signal to another device (a sink device) on the home network. An output-select button is used to specify which output plug is to be used by the source device.

Abstract: A method and apparatus for indicating information to a user of a palmtop computer. Illuminatable hard buttons are disclosed that are operable for performing functions. The hard buttons are selectively illuminated to indicate information to a user that relates to the function performed when the bard button is pressed. The selective illumination of hard buttons to indicate information that relates to the function that is performed when the hard button is pressed conveys information to the user in a manner that is easily understood by the user. In one embodiment, whether or not the button is illuminated and the color of the illumination, convey information about the function that is to be performed when the button is pressed.

Abstract: Embodiments of the present invention provide a striped or closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The striped or closed cell TMOSFET comprises a source region, a body region disposed above the source region, a drift region disposed above the body region, a drain region disposed above the drift region. A gate region is disposed above the source region and adjacent the body region. A gate insulator region electrically isolates the gate region from the source region, body region, drift region and drain region. The body region is electrically coupled to the source region.

Abstract: A method and circuit thereof for performing setup and hold (SUAH) testing on integrated circuits including, but not limited to SRAM, utilizing a relatively low number of test vectors, obviating the conventional requirement of writing to and reading back from each and every memory address. In one embodiment, a first test data signal of all zeros (0) is inputted to the input stage of the SRAM under test, and a subsequent second data signal of all ones (1) follows. In one embodiment, XOR/XNOR gates detect differences in data signals between the inputs and outputs of input stage latches/registers after clocking. In one embodiment, detected differences are combined into an error signal in combinational logic. In one embodiment, error signals are exported serially to a test system by a scan chain. Alternatively, in another embodiment, error signals are exported in parallel via individual output drivers.

Abstract: A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device.