Abstract: A communication circuit comprises a plurality of receivers to receive the serial data from multiple lanes of a communication channel. The receivers may convert data received from the lanes from a serial to parallel format. Decoders may identify characters recovered from the different lanes, which collectively may define a word of width (i.e., character width) related to the number of lanes. Logic may determine when at least one of a start-of-frame and an end-of-frame character has been received. Parsing circuitry may then determine valid characters of a received word based on their placement relative to a start-of-frame character and/or an end-of-frame character. A controller may control when to present recovered data to at least one of storage registers or an output port, based on the character type identified by the decoder, its placement, an amount of characters parsed, and the number of characters already stored.

Abstract: A variable latency elastic buffer comprises a plurality of memory locations in which to hold data. A write and read pointer may point to respective write and read addresses of the plurality of locations in which to write and read data. A controller may hold or increment the address of the read pointer upon determining that the amount of data within the buffer differs from a nominal fill level. In a particular embodiment, initialization circuitry may be operable to initialize the read and write addresses of the respective pointers responsive to an initialization request. The read and write addresses may differ from one another by an offset value equal to a value programmed for the nominal value.

Abstract: A true random number generator may comprise a multi-gigabit transceiver with a transceiver to receive a signal of predetermined source data. Recovery circuitry of the transceiver may be operable to recover data from the received signal. A controller may stress the recovery circuit to cause a portion of the data recovered to differ from the respective portion of the predetermined source data. An extractor may define numbers for a true random number sequence based on differences between the recovered data and the predetermined serial source data over an interval of time. In a particular example, the controller may influence at least one of the serial data transfer rate, the number of sequential same-state bits for the predetermined source data, and the stability of a clock signal to be recovered by a portion of the recovery circuit.

Abstract: A programmable logic device, in accordance with an embodiment of the present invention, may comprise a bus and a plurality of programmable masters configurable to interface the bus. A first portion of a memory may include configuration data operable to configure masters of the plurality, while a second portion of the memory may include access patterns to control when the different masters of the plurality may access the bus. An injection rate controller may control when a given master is to send data on the bus based on the access pattern associated with the master. A master controller may be operable to write the access patterns for the masters to the second portion of the configuration memory.

Abstract: A method of modeling a design in a high level modeling system that supports unidirectional data flow, may comprise identifying a bus-block to represent a connectivity of a bi-directional bus in an system. The bus-block may be represented in serial relationship with the bus. Taps may interface the bus via the bus-block. During simulation, the bus-block emulates behavior of a tri-state buffer in series with an input line for the tap interface. During synthesis, pairs of unidirectional input and output lines of opposite data-routing orientation, which may emulate bus ports to the bus-block, may be collapsed to a single bus port. The synthesis may further generate a netlist that may dispose a tri-state buffer between a tap input and the bus. The netlist may also represent layout of the tri-state buffer for driving an output of the tap.

Abstract: A programmable logic device (PLD) includes a plurality of configurable resources, a programmable interconnect having a plurality of signal lines for providing a number of dedicated signal paths between any of the configurable resources, and a subway routing system having a shared subway bus coupled to the signal lines of the programmable interconnect at a plurality of connection points by a plurality of corresponding subway ports. The subway routing system, which provides alternate routing resources for the programmable interconnect, may be used to route different signals between different configurable resources at different times.

Abstract: The performance of a serial data transceiver in a programmable logic device may be determined by applying a stress sequence of sequential data to a receiver of the transceiver, comparing the received data to reference data and determining the number of errors.

Abstract: In configuring a programmable logic device, first configurable resources of the programmable logic device may be configured as a boot-strap configurator dependent on data in a first portion of configuration memory. After configuring the first configurable resources, data previously stored in a buffer of the programmable logic device may be retrieved to overwrite at least a portion of the configuration memory associated with the boot-strap configurator.

Abstract: A programmable logic device may comprise a metric circuit operable to repeatedly perform a function and emit a first signal dependent upon its advancement into the function. A comparator may compare the first signal from the metric circuit to a predetermined reference signal. A controller may then selectively disable a portion of the programmable logic device dependent upon the results of the comparison. In a particular case, the weakened circuit may be a counter that repeatedly advances its count with a rate dependent upon an aging characteristic of a vulnerable element.

Abstract: A test circuit to test rise delay/fall delay performance on a semiconductor device may comprise a latch to latch data at its input responsive to a clock signal. The latch may source an output signal related to the data latched. A buffer chain may be configured to serially propagate the signal sourced by the latch from the latch output back to the clock input, as the clock signal. A reset/set input of the latch may be configured to receive a reset/set signal from an intermediate node of the buffer chain.

Abstract: A thyristor memory device may comprise a capacitor electrode formed over a base region of the thyristor using a replacement gate process. During formation of the thyristor, a base-emitter boundary may be aligned relative to a shoulder of the capacitor electrode. In a particular embodiment, the replacement gate process may comprise defining a trench in a layer of dielectric over semiconductor material. Conductive material for the electrode may be formed over the dielectric and in the trench. It may further be patterned to form a shoulder for the electrode that extends over regions of the dielectric over a base region for the thyristor. The extent of the shoulder may be used to pattern the dielectric and/or to assist alignment of implants for the base and emitter regions of the thyristor.

Abstract: An interconnect assembly to electrically interconnect one or more integrated circuits to an electronic device may comprise a base package to couple to a circuit board of the electronic device. A terminal mezzanine package may support the integrated circuit(s) above the base package. A first set of conductors of a first material and design carry low-frequency signals between the base and terminal connector packages. A second set of conductors of a second material and design carry high-frequency signals. In particular embodiments the base package may comprise a base mezzanine integrating one or more additional integrated circuits and intermediate mezzanines supporting one or more additional integrated circuits each and enabling multi-story modular interconnection structures. In particular embodiments, the second set of conductors may comprise columns of compressible polymer compound embedded with metallized particles, and the columns may be dispersed amongst pins and sockets of a pin-grid array.

Abstract: In a method of processing a semiconductor device, a silicide-blocking layer may be formed over a semiconductor material. After defining the silicide-blocking layer, impurities may be implanted into portions of the semiconductor material as defined by the silicide-blocking layer. After the implant, silicide may be formed in a surface region of the semiconductor material as permitted by the silicide-blocking layer. Regions of the impurity implant may comprise boundaries that are related to the outline of the silicide formed thereover. In a further embodiment, the implant may define a base region to a thyristor device. The implant may be performed with an angle of incidence to extend portions of the base region beneath a peripheral edge of the blocking mask. Next, an anode-emitter region may be formed using an implant of a substantially orthogonal angle of incidence and self-aligned to the mask.

Abstract: A method of planarizing a substrate employs two separate chemical mechanical polishing (CMP) steps. In the first CMP step, the substrate is polished using a first CMP slurry solution and a polishing pad. A diluting solution is then applied to the polishing pad to remove slurry of the first CMP step. In the second CMP step, after applying the diluting solution to the polishing pad to remove the first slurry, second CMP slurry solution is applied to the polishing pad to facilitate additional planarization of the substrate. In a particular embodiment of this invention, the diluting solution comprises a buffer solution having a pH level corresponding to a pH level of one of the first or second CMP slurry solution. In accordance with another aspect of this embodiment, a plurality of different diluting solutions are applied to the polishing pad intermediate the respective first and second CMP steps.

Abstract: An electrode and capacitor structure, and methods of manufacture thereof, are disclosed for a semiconductor device. The capacitor includes a dielectric layer sandwiched between opposing first and second electrically conductive electrodes. At least one of the electrodes includes a thin, oxygen-annealed, refractory metal nitride barrier layer disposed adjacent the dielectric. Preferabaly, the barrier comprises two thin layers of seperately oxygen-annealed, refractory metal nitride. In particular methods of manufacturing the electrode and capacitor structures, a single process chamber is used for both fabrication of the barrier layer(s) and deposition of overlying metalization for the electrode. The barrier layer, in one particular embodiment, is formed from precursor gases of titanium nitride and exposure to an oxidizing gas such as oxygen, ozone or nitrous oxide.

Abstract: The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a CMP process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chemical is a strong base chemical, like KOH, or potassium hydroxide. Moreover, the CMP process utilizes a system of closely regulating the timing of the two chemical processes. Specifically, during a first time period, both chemicals are applied; thus providing a given speed of the chemical removal of tungsten material. During a second time period, the KOH is removed, so as to slow down the chemical action and facilitate a greater degree of planarization.

Abstract: The present invention relates to integrated circuits (ICs) fabrication. Particularly, there is a cmp process which incorporates small quantities of two chemicals. The first chemical is the standard slurry mixtures, like water, aluminum-oxide and hydrogen-peroxide mixed into a slurry. The second chemical is a strong base chemical, like KOH, or potassium hydroxide. Moreover, the cmp process utilizes a system of closely regulating the timing of the two chemical process. Specifically, during a first time period, both chemicals are applied; thus increasing speed of the chemical removal of tungsten material. During a second time period, the KOH is removed, thus slowing down the chemical action and importantly achieving a greater degree of planerization than is capable by the two chemical first time period.

Abstract: A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

Abstract: A method of planarizing a substrate employs two separate chemical mechanical polishing (CMP) steps. In the first CMP step, the substrate is polished using a first CMP slurry solution and a polishing pad. A diluting solution is then applied to the polishing pad to remove slurry of the first CMP step. In the second CMP step, after applying the diluting solution to the polishing pad to remove the first slurry, second CMP slurry solution is applied to the polishing pad to facilitate additional planarization of the substrate. In a particular embodiment of this invention, the diluting solution comprises a buffer solution having a pH level corresponding to a pH level of one of the first or second CMP slurry solution. In accordance with another aspect of this embodiment, a plurality of different diluting solutions are applied to the polishing pad intermediate the respective first and second CMP steps.

Abstract: A wire serves as a gettering material which is wire-bonded to electrical connections which lead outside of a vacuum sealed package. The wire can be activated to create and maintain a high integrity vacuum environment. The "getter" can be either heat activated or evaporated by the passing of an AC or DC current through the wire.