Patents Represented by Attorney Walter D. Fields
  • Patent number: 5899749
    Abstract: A method of etching an oxide/poly/oxide sandwich structure in which both oxide layers are anisotropically etched, and the poly layer is also isotropically etched to recess the poly from the edge of the contact walls. The oxide etch can be done using oxide to nitride etch stop technology. The process is an in situ etch, that is, a single parallel plate plasma reactor is employed.
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: May 4, 1999
    Assignee: Micron Technology, Inc.
    Inventors: David S. Becker, Guy T. Blalock
  • Patent number: 5894266
    Abstract: A remote intelligent communications device includes a primary RF communications port and an alternative modem communications port. The remote intelligent communications device receives configuration data for configuring the alternative modem communications port. The remote intelligent communications device obtains information data concerning a select attribute of an associated object. The information data is stored within internal memory of the remote intelligent communications device. Thereafter, the stored information data is retrieved, per one embodiment via the alternative modem port, from the remote intelligent communications device and analyzed for drawing conclusions regarding the select attribute of the associated object. Preferably, the remote intelligent communications device also includes a navigation (e.g. GPS) receiver that obtains navigation data, which navigation data is also stored within the internal memory of the remote intelligent communications device.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: April 13, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Cliff Wood, Jr., David K. Ovard, George E. Pax, John R. Tuttle
  • Patent number: 5880036
    Abstract: A process for controlling the etch of a silicon dioxide layer at a high etch rate and high selectivity with respect to silicon nitride, particularly in a multilayer structure, by maintaining various portions of the etch chamber at elevated temperatures.
    Type: Grant
    Filed: November 15, 1993
    Date of Patent: March 9, 1999
    Assignee: Micron Technology, Inc.
    Inventors: David S. Becker, Guy T. Blalock, Lyle D. Breiner
  • Patent number: 5868870
    Abstract: A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.
    Type: Grant
    Filed: February 11, 1997
    Date of Patent: February 9, 1999
    Assignee: Micron Technology, Inc.
    Inventors: Pierre C. Fazan, Martin C. Roberts, Gurtej S. Sandhu
  • Patent number: 5733383
    Abstract: A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.
    Type: Grant
    Filed: December 13, 1994
    Date of Patent: March 31, 1998
    Assignee: Micron Technology, Inc.
    Inventors: Pierre C. Fazan, Martin C. Roberts, Gurtej S. Sandhu
  • Patent number: 5734226
    Abstract: A wire serves as a gettering material which is wire-bonded to electrical connections which lead outside of a vacuum sealed package. The wire can be activated to create and maintain a high integrity vacuum environment. The "getter" can be either heat activated or evaporated by the passing of an AC or DC current through the wire.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: March 31, 1998
    Assignee: Micron Technology, Inc.
    Inventor: David A. Cathey
  • Patent number: 5700580
    Abstract: A method is provided for forming a nitride spacer, in which a layer of oxide is grown superjacent a substrate and the semiconductor features disposed thereon. A layer of nitride is deposited superjacent the oxide layer, and a major horizontal portion of the nitride layer anisotropically etched with an ionized fluorocarbon compound. The remainder of the horizontal portion of the nitride layer is removed with NF.sub.3 ions in combination with ionized halogen-containing compound, thereby creating nitride spacers adjacent the features.
    Type: Grant
    Filed: September 7, 1994
    Date of Patent: December 23, 1997
    Assignee: Micron Technology, Inc.
    Inventors: David S. Becker, David J. Keller