Abstract: A thermal interface for IC chip cooling is provided. One embodiment of the thermal interface includes a thermally conductive liquid or paste-like metal(s) disposed within a flexible, thermally conductive enclosure. The enclosure is adapted to be placed between an IC chip and a heat sink to enhance heat transfer from the chip to the heat sink, thereby enabling quicker and more efficient cooling of the chip than can be achieved by conventional techniques. In several embodiments, the thermal interface is held in place by mechanical pressure rather than by bonding, which further facilitates inspection and repair of the IC device.

Abstract: A technique for forming a sub-0.05 &mgr;m channel length double-gated/double channel MOSFET structure having excellent short-channel characteristics as well as the double-gated/double channel MOSFET structure itself is provided herein. The inventive technique utilizes a damascene process for the fabrication of a MOSFET device with double-gate/double channel structure. The gates are present on opposite sides of a silicon film having a vertical thickness of about 80 nm or less which is present in the gate region. The silicon film serves as the vertical channel regions of the structure and connects diffusion regions that are abutting the gate region to each other. In the inventive device, the current is double that of a conventional planar MOSFET with the same physical width due to its dual channel feature.

Abstract: The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.

Abstract: An optical receiver circuit including a plurality of PIN diodes, each associated with a dedicated element transimpedance amplifier, the outputs of the element transimpedance amplifiers being connected to a summing amplifier which sums the voltages output from the element transimpedance amplifiers. The optical receiver circuit provides the same output voltage value as a single large PIN diode having an active area comparable to the sum of the active areas of the smaller PIN diodes, and thus has the same high sensitivity as the single large PIN diode but a much wider bandwidth.

Abstract: The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.

Abstract: A structure (e.g., field effect transistor) and a method for making the structure, include a substrate having a source region, a drain region, and a channel region therebetween, an insulating layer disposed over the channel region, the insulating layer including a layer including aluminum nitride disposed over the channel region, and a gate electrode disposed over the insulating layer.

Abstract: An electrically adjustable phase-shifting device is arranged on a substrate comprising at least a first waveguide designed for guiding optical signals and a thermoelectric element arranged adjacent to the first waveguide in order to shift the phase of an optical signal in the first waveguide by means of a thermo-optic effect according to a control voltage applied to the thermoelectric element. In one embodiment, the thermoelectric element is a Peitier element which comprises at least first and second electrically conducting segments which are serially connected, the first and second elements alternating consecutively.

Abstract: Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias.

Abstract: A method of forming a silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) device is provided in which an implanted back-gate is formed into a Si-containing layer of an SOI wafer. The implanted back-gate thus formed is capable of controlling the threshold voltage of a polysilicon-containing front-gate which is formed over a portion of the implanted back-gate region. The implanted back-gate functions as a dynamic threshold voltage control system in the SOI MOSFET device because it is suitable for use during circuit/system active periods and during circuit/system idle periods.

Abstract: A method and structure that forms a multilayer nanoparticle thin film assembly begins by functionalizing a substrate with functional molecules. Next, the invention replaces a stabilizer on a bottom surface of the first nanoparticles with the functional molecules via surface ligand exchange to make a first nanoparticle layer on the substrate. The invention then replaces the stabilizer on a top surface of the first nanoparticle layer with functional molecules via surface ligand exchange. The invention replaces the stabilizer on a bottom surface of the second nanoparticles with the functional molecules via surface ligand exchange to make a second nanoparticle layer on the first nanoparticle layer. Lastly, the invention repeats the previous steps and forms additional nanoparticle layers.

Abstract: A method (and resultant structure) of forming a semiconductor device, includes forming a metal-back-gate over a substrate and a metal back-gate, forming a passivation layer on the metal back-gate to prevent the metal back-gate from reacting with radical species, and providing an intermediate gluing layer between the substrate and the metal back-gate to enhance adhesion.

Abstract: An integrated circuit structure is disclosed that comprises a pair of capacitors, each having metal plates separated by an insulator, and metal gate semiconductor transistors electrically connected to the capacitors. The metal gate of the transistors and one of the metal plates of each of the capacitors comprise the same metal level in the integrated circuit structure. More specifically, each of the capacitors comprise a vertical capacitor having an upper metal plate vertically over a lower metal plate and each metal gate of the transistors and each upper metal plate of the capacitors comprise the same metal level in the integrated circuit structure.

Abstract: A semiconductor structure (and method for forming) having transistors having both metal gates and polysilicon gates on a single substrate in a single process is disclosed. The method forms a gate dielectric layer on the substrate and forms the metal seed layer on the gate oxide layer. The method patterns the metal seed layer to leave metal seed material in metal gate seed areas above the substrate. Next, the method patterns a polysilicon layer into polysilicon structures above the substrate. Some of the polysilicon structures comprise sacrificial polysilicon structures on the metal gate seed areas and the remaining ones of the polysilicon structures comprise the polysilicon gates. The patterning of the polysilicon gates forms the sacrificial gates above all the metal gate seed areas. Following that, the invention forms sidewall spacers, and source and drain regions adjacent the polysilicon structures.

Abstract: An electrically tunable coupler device is disposed on a substrate comprising a first and a second waveguide, for guiding optical signals. The coupler device comprises a heater element disposed adjacent the first waveguide for thermo-optically shifting the phase of the optical signal in the first waveguide in response to a control voltage applied to the heater element. The heater element is disposed in an interaction region of the optical signals, such that, within the interaction region, a temperature gradient across the first and the second waveguide is generated in dependence on the applied control voltage. A heat sink element can be disposed adjacent the second waveguide to absorb thermal energy from the heater element. This device can be fabricated at reduced cost and in increased packing density and is usable e.g. in directional couplers, Mach-Zehnder interferometers, optical ring resonators, IIR filters, or optical modulators.

Abstract: A structure and a method of manufacturing a double-gate metal oxide semiconductor transistor includes forming a laminated structure having a single crystal silicon channel layer and insulating oxide and nitride layers on each side of the single crystal silicon channel, forming openings in the laminated structure, forming drain and source regions in the openings, doping the drain and source regions, forming a mask over the laminated structure, removing portions of the laminated structure not protected by the mask, removing the mask and the insulating oxide and nitride layers to leave the single crystal silicon channel layer suspended from the drain and source regions, forming an oxide layer to cover the drain and source regions and the channel layer, and forming a double-gate conductor over the oxide layer such that the double-gate conductor includes a first conductor on a first side of the single crystal silicon channel layer and a second conductor on a second side of the single crystal silicon channel layer.

Abstract: The present invention is directed to a microelectric device and especially a Field effect transistor comprising a source, drain, channel, an insulating layer overlying said channel containing at least one closed cage molecule, said closed cage molecule being capable of exhibiting a Coulomb blockade effect upon application of a voltage between said source and drain. Two different microelectronic devices are described containing the closed cage molecule, a logic cell and a memory cell.

Abstract: A high efficiency light emitting diode (LED) driver circuit utilizes a capacitor to regulate the LED driving current. The voltage across the capacitor is monitored to maintain a preselected low threshold voltage on the capacitor, which determines the LED optical emission intensity. The capacitor provides the LED driver current by discharging through the LED during transmission intervals, and the power supply for the device is used only to maintain the capacitor charge level. The LED driver circuit accordingly operates at high efficiency with low power consumption. The LED driver current can be regulated by changing the low and high threshold voltages of the capacitor pump controller, thereby to control the optical intensity of the LED.

Abstract: A memory storage device is provided that includes a storage cell having a changeable magnetic region. The changeable magnetic region includes a material having a magnetization state that is responsive to a change in temperature. The memory storage device also includes a heating element. The heating element is proximate to the storage cell for selectively changing the temperature of the changeable magnetic region of said storage cell. By heating the storage cell via the heating element, as opposed to heating the storage cell by directly applying current thereto, more flexibility is provided in the manufacture of the storage cells.

Abstract: A method (and resultant structure) for forming a metal silicide contact on a silicon-containing region having controlled consumption of said silicon-containing region, includes implanting Ge into the silicon-containing region, forming a blanket metal-silicon mixture layer over the silicon-containing region, reacting the metal-silicon mixture with silicon at a first temperature to form a metal silicon alloy, etching unreacted portions of the metal-silicon mixture layer, forming a blanket silicon layer over the metal silicon alloy layer, annealing at a second temperature to form an alloy of metal-Si2, and selectively etching the unreacted silicon layer.

Abstract: A laminar structure upon a substrate is formed from a) a lattice layer comprising DNA (deoxyribonucleic acid) segments arranged to form cells of the lattice layer, and b), at least one nanoparticle being disposed within each cell of the lattice layer. The nanoparticles are preferably of substantially uniform diameter not exceeding 50 nanometers. A coating may be applied to adhere the the particles to the substrate and to maintain their substantially uniform spaced-apart relationship. The DNA lattice layer is fabricated using known automated synthetis methods, and is designed to contain specific nucleotide base sequences which cause the DNA to form an ordered array of openings, or lattice cells, by self-assembly. Self-assembly of the DNA lattice may be at an air-liquid interface, or in solution. A preferred embodiment is a magnetic storage medium in which the particles are magnetic particles with diameters in the range of 5-20 nm.