Abstract: A variable frequency multi-phase oscillator for providing multi-phase signals is disclosed. The variable frequency multi-phase oscillator includes a correlator, a plurality of delay cells, and a NOR circuit. Each delay cell includes a current supply, a capacitor, a comparator, a switch, and a logic unit. The plurality of delay cells generate the multi-phase signals that are phase correlated within a large frequency range. The frequency and duty cycles of the multi-phase signals are adjustable.

Abstract: The present invention is a telecommunication device with an auto-configurable capability that supports both serial and parallel data interfaces. The telecommunication device can transfer configuration data through a serial interface such as I2C interface and a parallel interface such as UPI. The telecommunication device can auto-configure through the I2C interface in master mode. The selectable configuration data stored in a second memory device is fetched by the telecommunication device through the I2C interface.

Abstract: The present invention is a DC/AC inverter for converting a DC supply voltage signal to an AC voltage signal. The DC/AC inverter includes a drive circuit, a switch circuit, a transformer circuit and an auxiliary circuit. The drive circuit provides a first drive signal and a second drive signal. The switch circuit includes a high-side transistor for receiving the first drive signal from the drive circuit and a low-side transistor for receiving the second drive signal from the drive circuit. The switch circuit further receives the DC supply voltage signal and generates a voltage signal. The transformer circuit receives the voltage signal from the switch circuit and transforms it to the AC voltage signal. The auxiliary circuit adjusts a gate-source voltage of the high-side transistor and thus enables the DC/AC inverter to be applicable to a wide DC voltage supply range.

Abstract: A current-mode DC-to-DC converter operating in a high frequency is disclosed. The current-mode DC-to-DC converter includes an inductor, a power switch, an oscillator, an adder without internal feedback loop, an error amplifier, a comparator, a compensation unit and a driver. The adder adds a ramp signal from the oscillator directly to a voltage signal relative to a current flowing through the power switch and generates a sum signal based upon match between internal components in the oscillator and the adder.

Abstract: A power management device for enabling multiply power sources to supply power to a load. The power management device includes a plurality of switches and a control logic. The plurality of switches are coupled to a plurality of power sources respectively and each switch coupled to each power source. The control logic is capable of selecting a set of switches among the plurality of switches to cooperate in a time-divided fashion to allow the power sources to provide power to the load. The set of switches is selected based on an electrical requirement of the load and an electrical condition of each switch.

Abstract: A voltage regulator for a static random access memory operating either in a standby mode or a operation mode is provided. The voltage regulator includes a reference voltage generating circuit for generating a reference voltage, a first control circuit connected to the reference voltage generating circuit for providing power supply during the standby mode of the SRAM, and a second control circuit connected to the reference voltage generating circuit for providing power in response to an enabling signal during the operation mode of the SRAM.

Abstract: A tunable band pass filter is provided. The tunable band pass filter includes a band pass filter and a plurality of switches coupled to the band pass filter. The band pass filter includes a plurality of transconductors and a plurality of capacitors. The tunable band pass filter can be configured as a complex band pass filter or as a tuning device for tuning the center frequency of the complex band pass filter depending on the operation of the plurality of switches. The tuning device includes at least one tuning integrator and a comparator. The tuning integrator includes at least one transconductor and a capacitor. The transconductor is selected via the plurality of switches from the plurality of transconductors and the capacitor is selected via the plurality of switches from said plurality of capacitors. The selected transconductor and the selected capacitor determinines the center frequency of the band pass filter.

Abstract: A compressed pattern matching based on LZW compressed sequences with a simple bitmap-based realization of the Amir-Benson-Farach algorithm is provided. A suffix trie for a searched pattern is determined and a LZW trie is constructed for a compressed data. For each data chunk in the compressed data a variety of information is determined and a node is added to the LZW trie. The queries used to determine the information are implemented through bitmaps, and allowing identification of all occurrence of the searched pattern.

Abstract: The present invention provides a GPS receiver which is capable of computing a local time reference without employing a RTC circuitry and employing a nonvolatile storing unit to store backup navigation data, wherein the local time reference and the backup navigation data can be used to reduce the TTFF of the GPS receiver. The GPS receiver includes a nonvolatile storing unit and a positioning unit. The positioning unit is capable of retrieving the backup navigation data from the nonvolatile storing unit and computing a local time reference after said GPS receiver is powered up. The positioning unit is further capable of employing the backup navigation data and the local time reference to computing the position of the GPS.

Abstract: A RF variable gain amplifier with an extended linear tuning range is disclosed. The variable gain amplifier employs a wide swing cascode mirror formed by two cascode transistors and two gain transistors. The two cascode transistors track each other, so are the two gain transistor. The gain transistors operate on the saturation region.

Abstract: A system and method for forwarding data packets with quality of service and rate control. A plurality of data packets are received from a plurality of sources. The header information of each data packet is extracted and compared against a plurality of tables, and then new header information is assembled based upon the comparison results. The data packets have their headers replaced by the new header information on the fly before being sent to their destinations, or the new header information may be dropped if certain conditions are met.

Abstract: A method for using a single pin to support both power input and power control functions for an integrated circuit, wherein the integrated circuit is in communication with a system. The method includes receiving at the pin a power input signal from the system, generating a power control signal based on the power input signal through a control signal generating circuit, and sending the power control signal to the integrated circuit.

Abstract: An apparatus and method for detecting battery pack voltage is disclosed. The voltage detection apparatus includes a plurality of selectors for providing a cell voltage of a predetermined cell, a detector buffer for receiving the cell voltage of the predetermined cell and supplying an intermediate voltage, a data process circuit for processing the intermediate voltage to acquire a voltage value indicative of the cell voltage of the predetermined cell, wherein each selector includes a plurality of switches and a plurality of level shifters, each switch being controlled by one of the plurality of level shifters to operate with a safe gate-source voltage, source-bulk voltage and reverse-biased body diode.

Abstract: The present invention is a LDO voltage regulator circuit with common-mode feedback. The LDO voltage regulator includes an error amplifier with a common-mode feedback unit, a pass device and a compensation circuit. A signal from the pass device acts as an input signal to the error amplifier and is compared with another input signal, producing a differential signal. The differential signal is amplified and then provided to the pass device. A capacitor in the compensation unit provides frequency compensation to the LDO voltage regulator. The common-mode feedback unit incorporated into the error amplifier greatly improves a slew rate of a gate voltage of the pass device.

Abstract: An analog to digital converter (ADC) with interference rejection capability and method thereof are disclosed. The ADC includes a threshold generator, a comparator circuit, a counter and an integrator. By comparing a signal with positive and negative threshold signals from the threshold generator, the comparator circuit converts the signal from analog to digital based on the result of the comparison. The counter counts a percentage of the digital signal and generates a bit signal based on the counted percentage. In response to the bit signal, the integrator supplies a control signal to the threshold generator to regulate the positive and negative threshold signals so as to maintain the counted percentage at a predetermined percentage threshold.

Abstract: A frequency synthesizer with a single PLL and multiple SSB mixers is presented. The frequency synthesizer includes a single PLL outputting a reference signal that is fed to a plurality of dividers coupled in sequence. The outputs from the dividers are mixed by the SSB mixers to produce signals with different frequencies. These signals with different frequencies can be selected through use of multiple selectors.