Patents Represented by Attorney, Agent or Law Firm Warren L. Franz
  • Transistors with recessed active trenches for increased effective gate width
    Patent number: 7642144
    Abstract: A method of manufacturing a semiconductor device having recessed active trenches by providing a substrate with STI and active regions, forming a first oxide layer on the substrate, forming an nitride layer on the first oxide layer, employing a photolithographic process to create at least one recessed active trench through the first oxide layer and the nitride layer and into the substrate to create an isolation region, wherein the at least one trench is perpendicular to at least one gate structure in an active area of the substrate, layering the trench with a second oxide layer, removing the first oxide layer and second oxide layer, forming a third oxide layer on the planar substrate with recessed active trench, and forming the at least one circuitous gate structure on the third oxide layer connecting at least one electronic source and drain.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: January 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Andrew Marshall, Gabriel George Barna
  • Methods for forming gate electrodes for integrated circuits
    Patent number: 7642153
    Abstract: A method of forming an integrated circuit can include the steps of providing a substrate having a semiconducting surface and forming a plurality of semiconducting multilayer features on the substrate surface, the features comprising a base layer and a compositionally different capping layer on the base layer. The method can also include forming spacers on sidewalls of the plurality of features, etching the capping layer, where the etching comprises selectively removing the capping layer, removing at least a portion of the base layer to form a plurality of trenches, and forming gate electrodes in the trenches.
    Type: Grant
    Filed: October 23, 2007
    Date of Patent: January 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Michael F. Pas
  • Method of mapping lithography focus errors
    Patent number: 7642021
    Abstract: The present application is directed to a method for determining photolithography focus errors during production of a device. The method comprises providing a substrate and forming a photoresist pattern on the substrate. The photoresist pattern comprises a device pattern and one or more blocking scheme patterns. The process further comprises performing a device manufacturing process using the photoresist pattern as a mask to form sensor windows on the substrate. One or more focus error sensors are formed in the sensor windows. Focus errors are determined using the focus error sensors. Other embodiments of the present application are directed to wafers comprising one or more focus error sensors positioned in sensor windows.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: January 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Guohong Zhang, Stephen J. DeMoor
  • Support structure for low-k dielectrics
    Patent number: 7642649
    Abstract: A semiconductor device employs a support structure to mitigate damage to dielectric layers having a low dielectric constant (k). The semiconductor device includes at least one inter-level dielectric layer (ILD) comprising a material having a low dielectric constant (k), and at least one support structure disposed within the low-k dielectric layer. The support structure mitigates damage of the semiconductor device by providing a mechanically stable interface between two layers in the semiconductor device.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: January 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Masood Murtuza
  • Method to improve performance of secondary active components in an esige CMOS technology
    Patent number: 7642197
    Abstract: According to various embodiments, there are eSiGe CMOS devices and methods of making them. The method of making a substrate for a CMOS device can include providing a DSB silicon substrate including a first bonded to a second layer, wherein each layer has a (100) oriented surface and a first direction and a second direction and the first direction of the first layer is approximately aligned with the second direction of the second layer. The method can also include performing amorphization on a selected region of the first layer to form a localized amorphous silicon region and recrystallizing the localized amorphous silicon region across the interface using the second layer as a template, such that the first direction of the first layer in the selected region is approximately aligned with the first direction of the second layer.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: January 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Periannan Chidambaram, Angelo Pinto
  • Air gap in integrated circuit inductor fabrication
    Patent number: 7642619
    Abstract: A semiconductor device, such as an inductor, is formed with an air gap. A first level has an intra-metal dielectric layer including one or more inductor loops, one or more vias, and one or more copper bulkhead structures. An inter-level dielectric layer is formed over the first level. An extraction via is formed through the intra-metal dielectric layer and inter-level dielectric layer. An air gap is formed between inductor loops by removing portions of the intra-metal dielectric layer coupled to the extraction via using a supercritical fluid process, and forming a non-conformal layer to seal the extraction via. The air gap may be filled with an inert gas, like argon or nitrogen.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 5, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Phillip D. Matz, Stephan Grunow, Satyavolu Srinivas Papa Rao
  • Integrating high performance and low power multi-gate devices
    Patent number: 7638843
    Abstract: A semiconductor device comprises a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprises a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width of the second gate structure.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: December 29, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Weize W. Xiong, Cloves Rinn Cleavelin
  • Method and system for reducing charge damage in silicon-on-insulator technology
    Patent number: 7638412
    Abstract: According to one embodiment of the invention, a silicon-on-insulator device includes an insulative layer formed overlying a substrate and a source and drain region formed overlying the insulative layer. The source region and the drain region comprise a material having a first conductivity type. A body region is disposed between the source region and the drain region and overlying the insulative layer. The body region comprises a material having a second conductivity type. A gate insulative layer overlies the body region. This device also includes a gate region overlying the gate insulative layer. The device also includes a diode circuit conductively coupled to the source region and a conductive connection coupling the gate region to the diode circuit.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: December 29, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: James D. Gallia, Srikanth Krishnan, Anand T. Krishnan
  • Solid state heat pump
    Patent number: 7628021
    Abstract: In accordance with the invention, there are methods for transferring heat, for heating and cooling, and there is a solid state heat pump. The solid state heat pump can include a power supply that provides an electric field, a first metal layer, a dielectric layer disposed over the first metal layer, wherein the dielectric layer absorbs a first amount of heat upon application of the electric field and releases a second amount of heat upon alteration of the electric field, and wherein the second amount of heat is greater than the first amount of heat, and a second metal layer disposed over the dielectric layer. The alteration of the electric field can be achieved at least by one of reducing, removing, and/or reversing the polarity of the electric field. The solid state heat pump can also include a series resistor.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: December 8, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Joe Wayne McPherson
  • Doped WGe to form dual metal gates
    Patent number: 7629212
    Abstract: A method of fabricating a dual metal gate structures in a semiconductor device, the method comprising forming a gate dielectric layer above a semiconductor body, forming a work function adjusting layer on the dielectric gate layer in the PMOS region, depositing a tungsten germanium gate electrode layer above the work function adjusting material in the PMOS region, depositing a tungsten germanium gate electrode layer above the gate dielectric in the NMOS region annealing the semiconductor device, depositing a metal nitride barrier layer on the tungsten germanium layer, depositing a polysilicon layer over the metal nitride, patterning the polysilicon layer, the metal nitride layer, the tungsten germanium layer, work function adjusting layer and the gate dielectric layer to form a gate structure, and forming a source/drain on opposite sides of the gate structure.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: December 8, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Manfred Ramin, Mark R. Visokay, Michael Francis Pas
  • Open source/drain junction field effect transistor
    Patent number: 7615425
    Abstract: The disclosure herein pertains to fashioning an n channel junction field effect transistor (NJFET) and/or a p channel junction field effect transistor (PJFET) with an open drain, where the open drain allows the transistors to operate at higher voltages before experiencing gate leakage current. The open drain allows the voltage to be increased several fold without increasing the size of the transistors. Opening the drain essentially spreads equipotential lines of respective electric fields developed at the drains of the devices so that the local electric fields, and hence the impact ionization rates are reduced to redirect current below the surface of the transistors.
    Type: Grant
    Filed: August 15, 2006
    Date of Patent: November 10, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Joe R. Trogolo, Hiroshi Yasuda, Badih El-Kareh, Philipp Steinmann
  • Versatile system for optimizing current gain in bipolar transistor structures
    Patent number: 7615805
    Abstract: Disclosed are apparatus and methods for designing electrical contact for a bipolar emitter structure. The area of an emitter structure (106, 306, 400, 404) and the required current density throughput of an electrical contact structure (108, 308, 402, 406) are determined. A required electrical contact area is determined based on the required current density, and the electrical contact structure is then designed to minimize the required electrical contact area with respect to the emitter structure area.
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: November 10, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Joe R. Trogolo, Tathagata Chatterjee, Lily X. Springer, Jeffrey P. Smith
  • Thick oxide film for wafer backside prior to metalization loop
    Patent number: 7615386
    Abstract: A method for reducing wafer backside large particle contamination, comprising: performing front end of line processing of a memory device, depositing a thick oxide on the wafer backside so that at least pre-selected oxide thickness remains after back end of line processing is complete and performing the back end of line processing of the memory device.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: November 10, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Nhan Hanh Anderson
  • Activation of CMOS source/drain extensions by ultra-high temperature anneals
    Patent number: 7615458
    Abstract: A method of manufacturing a semiconductor device that includes forming a gate dielectric layer over a semiconductor substrate. A gate electrode is formed over the gate dielectric layer. A dopant is implanted into an extension region of the substrate, with an amount of the dopant remaining in a dielectric layer adjacent the gate electrode. The substrate is annealed at a temperature of about 1000° C. or greater to cause at least a portion of the amount of the dopant to diffuse into the semiconductor substrate.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: November 10, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Amitabh Jain, Manoj Mehrotra
  • Structure for dual work function metal gate electrodes by control of interface dipoles
    Patent number: 7612422
    Abstract: Exemplary embodiments provide structures for dual work function metal gate electrodes. The work function value of a metal gate electrode can be increased and/or decreased by disposing various electronegative species and/or electropositive species at the metal/dielectric interface to control interface dipoles. In an exemplary embodiment, various electronegative species can be disposed at the metal/dielectric interface to increase the work function value of the metal, which can be used for a PMOS metal gate electrode in a dual work function gated device. Various electropositive species can be disposed at the metal/dielectric interface to decrease the work function value of the metal, which can be used for an NMOS metal gate electrode in the dual work function gated device.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: November 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: James Joseph Chambers, Luigi Colombo, Mark Robert Visokay
  • Semiconductor device with improved contact fuse
    Patent number: 7612454
    Abstract: One aspect of the invention provides an integrated circuit(IC) [400b]. The IC comprises transistors [410b] and contact fuses [422b]. The contact fuses each comprise a conducting layer [424b], a frustum-shaped contact [426b] has a narrower end that contacts the conducting layer and a first metal layer [427b] that is located over the conducting layer. A wider end of the frustum-shaped contact contacts the first metal layer. The frustum-shaped contact has a ratio of an opening of the wider end to the narrower end that is at least about 1.2. The contact fuses each further include a heat sink [432b] that is located over and contacts the first metal layer.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: November 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Honglin Guo, Dongmei Lei, Brian Goodlin, Joe McPherson
  • Semiconductor device manufactured using a laminated stress layer
    Patent number: 7611939
    Abstract: There is presented a method of forming a semiconductor device. The method comprises forming gate structures including forming gate electrodes over a semiconductor substrate and forming spacers adjacent the gate electrodes. Source/drains are formed adjacent the gate structures, and a laminated stress layer is formed over the gate structure and the semiconductor substrate. The formation of the laminated stress layer includes cycling a deposition process to form a first stress layer over the gate structures and the semiconductor substrate and at least a second stress layer over the first stress layer. After the laminated layer is formed, it is subjected to an anneal process conducted at a temperature of about 900° C. or greater.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: November 3, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Manoj Mehrotra, Antonio L. P. Rotondaro, Puneet Kohli
  • Drive circuit and drain extended transistor for use therein
    Patent number: 7602019
    Abstract: A transistor comprises a source region of a first conductivity type and electrically communicating with a first semiconductor region. The transistor also comprises a drain region of the first conductivity type and electrically communicating with a second semiconductor region that differs from the first semiconductor region. An interface exists between the first semiconductor region and the second semiconductor region. The transistor also comprises a voltage tap region comprising at least a portion located in a position that is closer to the interface than the drain region. A mixed technology circuit is also described.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: October 13, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Sameer Pendharkar
  • Distributed element generator, method of generating distributed elements and an electronic design automation tool employing the same
    Patent number: 7596771
    Abstract: The present invention provides a distributed element generator for use with an electronic design automation tool. In one embodiment, the distributed element generator includes a parasitic element extractor configured to identify parasitic elements associated with a passive integrated circuit device having a surrounding layout environment. Additionally, the distributed element generator also includes a distributed parameter allocator coupled to the parasitic element extractor and configured to provide a distributed model of the passive integrated circuit device and allocate the parasitic elements within the distributed model based on the surrounding layout environment.
    Type: Grant
    Filed: May 10, 2005
    Date of Patent: September 29, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Isaac D. Cohen, Sergey F. Komarov
  • Dual metal gates for mugfet device
    Patent number: 7582521
    Abstract: Exemplary embodiments provide methods and structures for controlling work function values of dual metal gate electrodes for transistor devices. Specifically, the work function value of one of the PMOS and NMOS metal gate electrodes can be controlled by a reaction between stacked layers deposited on a gate dielectric material. The stacked layers can include a first-metal-containing material such as Al2O3, and/or AlN overlaid by a second-metal-containing material such as TaN, TiN, WN, MoN or their respective metals. The reaction between the stacked layers can create a metal gate material with a desired work function value ranging from about 4.35 eV to about 5.0 eV. The disclosed methods and structures can be used for CMOS transistors including MOSFET devices formed on a bulk substrate, and planar FET devices or 3-D MuGFET devices (e.g., FinFET devices) formed upon the oxide insulator of a SOI.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: September 1, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Husam Niman Alshareef, Weize Xiong